Magnetic random access memory

ABSTRACT

A read block is formed from a plurality of TMR elements stacked in the vertical direction. One terminal of each TMR element in the read block is connected to a source line through a read select switch. The source line extends in the Y-direction and is connected to a ground point through a column select switch. The other terminal of each TMR element is independently connected to a corresponding one of read/write bit lines. Each read/write bit line extends in the Y-direction and is connected to a read circuit through the column select switch.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 2001-390549, filed Dec.21, 2001, the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a magnetic random access memory(MRAM) which stores “1”- and “0”-data using a magnetoresistive effect.

[0004] 2. Description of the Related Art

[0005] In recent years, many memories which store data by new principleshave been proposed. One of them is a magnetic random access memory whichstores “1”- and “0”-data using a tunneling magnetoresistive (to bereferred to as TMR hereinafter) effect.

[0006] As a proposal for a magnetic random access memory, for example,Roy Scheuerlein et al, “A 10ns Read and Write Non-Volatile Memory ArrayUsing a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC2000Technical Digest, p. 128 is known.

[0007] A magnetic random access memory stores “1”- and “0”-data usingTMR elements. As the basic structure of a TMR element, an insulatinglayer (tunneling barrier) is sandwiched between two magnetic layers(ferromagnetic layers).

[0008] Data stored in the TMR element is determined on the basis ofwhether the magnetizing states of the two magnetic layers are parallelor anti-parallel. “Parallel” means that the two magnetic layers have thesame magnetizing direction. “Anti-parallel” means that the two magneticlayers have opposite magnetizing directions.

[0009] Normally, one (fixed layer) of the two magnetic layers has ananti-ferromagnetic layer. The anti-ferromagnetic layer serves as amember for fixing the magnetizing direction of the fixed layer. In fact,data (“1” or “0”) stored in the TMR element is determined by themagnetizing direction of the other (free layer) of the two magneticlayers.

[0010] When the magnetizing states in the TMR element are parallel, theresistance of the insulating layer (tunneling barrier) sandwichedbetween the two magnetic layers of the TMR element is minimized. Forexample, this state is defined as a “1”-state. When the magnetizingstates in the TMR element are anti-parallel, the resistance of theinsulating layer (tunneling barrier) sandwiched between the two magneticlayers of the TMR element is maximized. For example, this state isdefined as a “0”-state.

[0011] Currently, various kinds of cell array structures have beenexamined for a magnetic random access memory from the viewpoint ofincreasing the memory capacity or stabilizing write/read operation.

[0012] For example, currently, a cell array structure in which onememory cell is formed from one MOS transistor and one TMR element (or anMTJ (Magnetic Tunnel Junction) element) is known. Additionally, amagnetic random access memory which has such a cell array structure andstores 1-bit data using two memory cell arrays so as to realize stableread operation is also known.

[0013] However, in these magnetic random access memories, it isdifficult to increase the memory capacity. This is because one MOStransistor corresponds to one TMR element in these cell arraystructures.

BRIEF SUMMARY OF THE INVENTION

[0014] According to an aspect of the present invention, there isprovided a magnetic random access memory comprising: a plurality ofmemory cells which are stacked at a plurality of stages to store datausing a magnetoresistive effect; a read select switch commonly connectedto one terminal of each of the plurality of memory cells; and aplurality of bit lines arranged in correspondence with the plurality ofmemory cells and extending in a first direction, wherein each of theplurality of memory cells has the other terminal independently connectedto one of the plurality of bit lines.

[0015] According to an aspect of the present invention, there isprovided a read method-of a magnetic random access memory, the magneticrandom access memory having a read block formed from a plurality ofmemory cells which store data using a magnetoresistive effect, and aplurality of sense amplifiers arranged in correspondence with theplurality of memory cells, comprising: simultaneously and independentlysupplying a read current to the plurality of memory cells; detectingdata of the plurality of memory cells by the plurality of senseamplifiers on the basis of the read current; and simultaneouslyoutputting data of the plurality of sense amplifiers.

[0016] According to an aspect of the present invention, there isprovided a manufacturing method of a magnetic random access memory,comprising: forming a read select switch on a surface region of asemiconductor substrate; forming a first write word line extending in afirst direction on the read select switch; forming a first MTJ elementright above the first write word line; forming, right above the firstMTJ element, a first read/write bit line which is in contact with thefirst MTJ element and extends in a second direction perpendicular to thefirst direction; forming a second write word line extending in the firstdirection right above the first write word line; forming a second MTJelement right above the second write word line; and forming, right abovethe second MTJ element, a second read/write bit line which is in contactwith the second MTJ element and extends in the second direction.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0017]FIG. 1 is a circuit diagram related to a magnetic random accessmemory of Structural Example 1 of the present invention;

[0018]FIG. 2 is a circuit diagram related to the magnetic random accessmemory of Structural Example 1 of the present invention;

[0019]FIG. 3 is a circuit diagram related to a modification to themagnetic random access memory of Structural Example 1 of the presentinvention;

[0020]FIG. 4 is a sectional view related to the magnetic random accessmemory of Structural Example 1 of the present invention;

[0021]FIG. 5 is a sectional view related to the magnetic random accessmemory of Structural Example 1 of the present invention;

[0022]FIG. 6 is a plan view showing a TMR element of Structural Example1 and the layout near the TMR element;

[0023]FIG. 7 is a sectional view showing a structural example of the TMRelement;

[0024]FIG. 8 is a sectional view showing a structural example of the TMRelement;

[0025]FIG. 9 is a sectional view showing a structural example of the TMRelement;

[0026]FIG. 10 is a circuit diagram related to a magnetic random accessmemory of Structural Example 2 of the present invention;

[0027]FIG. 11 is a sectional view related to the magnetic random accessmemory of Structural Example 2 of the present invention;

[0028]FIG. 12 is a sectional view related to the magnetic random accessmemory of Structural Example 2 of the present invention;

[0029]FIG. 13 is a circuit diagram related to a magnetic random accessmemory of Structural Example 3 of the present invention;

[0030]FIG. 14 is a circuit diagram related to the magnetic random accessmemory of Structural Example 3 of the present invention;

[0031]FIG. 15 is a circuit diagram related to a modification to themagnetic random access memory of Structural Example 3 of the presentinvention;

[0032]FIG. 16 is a circuit diagram related to a modification to themagnetic random access memory of Structural Example 3 of the presentinvention;

[0033]FIG. 17 is a sectional view related to the magnetic random accessmemory of Structural Example 3 of the present invention;

[0034]FIG. 18 is a sectional view related to the magnetic random accessmemory of Structural Example 3 of the present invention;

[0035]FIG. 19 is a plan view showing a TMR element of Structural Example3 and the layout near the TMR element;

[0036]FIG. 20 is a circuit diagram related to a magnetic random accessmemory of Structural Example 4 of the present invention;

[0037]FIG. 21 is a sectional view related to the magnetic random accessmemory of Structural Example 4 of the present invention;

[0038]FIG. 22 is a sectional view related to the magnetic random accessmemory of Structural Example 4 of the present invention;

[0039]FIG. 23 is a circuit diagram related to a magnetic random accessmemory of Structural Example 5 of the present invention;

[0040]FIG. 24 is a sectional view related to the magnetic random accessmemory of Structural Example 5 of the present invention;

[0041]FIG. 25 is a sectional view related to the magnetic random accessmemory of Structural Example 5 of the present invention;

[0042]FIG. 26 is a circuit diagram related to a magnetic random accessmemory of Structural Example 6 of the present invention;

[0043]FIG. 27 is a sectional view related to the magnetic random accessmemory of Structural Example 6 of the present invention;

[0044]FIG. 28 is a sectional view related to the magnetic random accessmemory of Structural Example 6 of the present invention;

[0045]FIG. 29 is a circuit diagram related to a magnetic random accessmemory of Structural Example 7 of the present invention;

[0046]FIG. 30 is a sectional view related to the magnetic random accessmemory of Structural Example 7 of the present invention;

[0047]FIG. 31 is a circuit diagram related to a magnetic random accessmemory of Structural Example 8 of the present invention;

[0048]FIG. 32 is a sectional view related to the magnetic random accessmemory of Structural Example 8 of the present invention;

[0049]FIG. 33 is a view showing a circuit example of the write word linedriver/sinker;

[0050]FIG. 34 is a view showing a circuit example of the write bit linedriver/sinker;

[0051]FIG. 35 is a view showing a circuit example of the write bit linedriver/sinker;

[0052]FIG. 36 is a view showing a circuit example of the read word linedriver;

[0053]FIG. 37 is a view showing a circuit example of the read word linedriver;

[0054]FIG. 38 is a view showing a circuit example of the column decoder;

[0055]FIG. 39 is a view showing a circuit example of the column decoder;

[0056]FIG. 40 is a block diagram of a circuit example of the readcircuit;

[0057]FIG. 41 is a block diagram of a circuit example of the readcircuit;

[0058]FIG. 42 is a view showing a circuit example of the sense amplifier& bias circuit;

[0059]FIG. 43 is a view showing a circuit example of the senseamplifier;

[0060]FIG. 44 is a view showing a circuit example of the referencepotential generating circuit;

[0061]FIG. 45 is a view showing a circuit example of an differentialamplifier, the OP in FIGS. 42 and 44 and the S/A in FIG. 43;

[0062]FIG. 46 is a view showing a device structure to which themanufacturing method of the present invention is applied;

[0063]FIG. 47 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0064]FIG. 48 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0065]FIG. 49 is a plan view showing one step of the manufacturingmethod of the present invention;

[0066]FIG. 50 is a sectional view taken along a line L-L in FIG. 49;

[0067]FIG. 51 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0068]FIG. 52 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0069]FIG. 53 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0070]FIG. 54 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0071]FIG. 55 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0072]FIG. 56 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0073]FIG. 57 is a plan view showing one step of the manufacturingmethod of the present invention;

[0074]FIG. 58 is a sectional view taken along a line LVIII-LVIII in FIG.57;

[0075]FIG. 59 is a plan view showing one step of the manufacturingmethod of the present invention;

[0076]FIG. 60 is a sectional view taken along a line LX-LX in FIG. 59;

[0077]FIG. 61 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0078]FIG. 62 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0079]FIG. 63 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0080]FIG. 64 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0081]FIG. 65 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0082]FIG. 66 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0083]FIG. 67 is a plan view showing one step of the manufacturingmethod of the present invention;

[0084]FIG. 68 is a sectional view taken along a line LXVIII-LXVIII inFIG. 67;

[0085]FIG. 69 is a plan view showing one step of the manufacturingmethod of the present invention;

[0086]FIG. 70 is a sectional view taken along a line LXX-LXX in FIG. 69;

[0087]FIG. 71 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0088]FIG. 72 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0089]FIG. 73 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0090]FIG. 74 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0091]FIG. 75 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0092]FIG. 76 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0093]FIG. 77 is a plan view showing one step of the manufacturingmethod of the present invention;

[0094]FIG. 78 is a sectional view taken along a line LXXVIII-LXXVIII inFIG. 77;

[0095]FIG. 79 is a plan view showing one step of the manufacturingmethod of the present invention;

[0096]FIG. 80 is a sectional view taken along a line LXXX-LXXX in FIG.79;

[0097]FIG. 81 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0098]FIG. 82 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0099]FIG. 83 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0100]FIG. 84 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0101]FIG. 85 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0102]FIG. 86 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0103]FIG. 87 is a plan view showing one step of the manufacturingmethod of the present invention;

[0104]FIG. 88 is a sectional view taken along a line LXXXVIII-LXXXVIIIin FIG. 87;

[0105]FIG. 89 is a plan view showing one step of the manufacturingmethod of the present invention;

[0106]FIG. 90 is a sectional view taken along a line XL-XL in FIG. 90;

[0107]FIG. 91 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0108]FIG. 92 is a sectional view showing one step of the manufacturingmethod of the present invention;

[0109]FIG. 93 is a plan view showing one step of the manufacturingmethod of the present invention;

[0110]FIG. 94 is a sectional view taken along a line XCIV-XCIV in FIG.93;

[0111]FIG. 95 is a circuit diagram showing a modification to StructuralExample 1;

[0112]FIG. 96 is a circuit diagram showing a modification to StructuralExample 1;

[0113]FIG. 97 is a sectional view showing a modification to StructuralExample 1;

[0114]FIG. 98 is a sectional view showing a modification to StructuralExample 1;

[0115]FIG. 99 is a sectional view showing a modification to StructuralExample 1;

[0116]FIG. 100 is a sectional view showing a modification to StructuralExample 1;

[0117]FIG. 101 is a circuit diagram showing a modification to StructuralExample 2;

[0118]FIG. 102 is a sectional view showing a modification to StructuralExample 2;

[0119]FIG. 103 is a sectional view showing a modification to StructuralExample 2;

[0120]FIG. 104 is a sectional view showing a modification to StructuralExample 1;

[0121]FIG. 105 is a sectional view showing a modification to StructuralExample 1;

[0122]FIG. 106 is a circuit diagram showing a modification to StructuralExample 3;

[0123]FIG. 107 is a circuit diagram showing a modification to StructuralExample 3;

[0124]FIG. 108 is a sectional view showing a modification to StructuralExample 3;

[0125]FIG. 109 is a sectional view showing a modification to StructuralExample 3;

[0126]FIG. 110 is a sectional view showing a modification to StructuralExample 3;

[0127]FIG. 111 is a sectional view showing a modification to StructuralExample 3;

[0128]FIG. 112 is a circuit diagram showing a modification to StructuralExample 4;

[0129]FIG. 113 is a sectional view showing a modification to StructuralExample 4;

[0130]FIG. 114 is a sectional view showing a modification to StructuralExample 4;

[0131]FIG. 115 is a sectional view showing a modification to StructuralExample 4; and

[0132]FIG. 116 is a sectional view showing a modification to StructuralExample 4.

DETAILED DESCRIPTION OF THE INVENTION

[0133] A magnetic random access memory of an aspect of the presentinvention will be described below in detail with reference to theaccompanying drawings.

[0134] 1. Cell Array Structure

[0135] First, a cell array structure of a magnetic random access memoryof an aspect of the present invention will be described below in detail.

(1) STRUCTURAL EXAMPLE 1

[0136] In Structural Example 1, one read block is formed from four TMRelements. In this example, a case wherein the number of TMR elements inone read block is four will be described. However, the number of TMRelements in one read block is not limited to four and can be freely set.

[0137] {circle over (1)} Circuit Structure

[0138] The circuit structure will be described first.

[0139]FIG. 1 shows main part of a magnetic random access memory asStructural Example 1 of the present invention. FIG. 2 shows an exampleof a column select switch shown in FIG. 1.

[0140] A memory cell array 11 has a plurality of TMR elements 12 arrayedin the X-, Y- and Z-directions. The Z-direction means a directionperpendicular to the X- and Y-directions, i.e., a directionperpendicular to the memory cell array plane.

[0141] In this example, the memory cell array 11 has a cell arraystructure formed from j TMR elements 12 arranged in the X-direction, nTMR elements 12 arranged in the Y-direction, and four TMR elements(MTJ1, MTJ2, MTJ3 and MTJ4) 12 stacked in the Z-direction.

[0142] In this example, the number of TMR elements 12 stacked in theZ-direction is four. However, the number of TMR elements is notparticularly limited as long as the number is two or more.

[0143] The four TMR elements 12 stacked in the Z-direction construct oneread block BKik (i=1, 2, . . . , j, k=1, 2, . . . , n). In fact, thefour TMR elements 12 in the read block BKik overlap one another in thedirection (Z-direction) perpendicular to the memory cell array plane.

[0144] In this example, one row is constructed by j read blocks BKikarranged in the X-direction. The memory cell array 11 has n rows. Inaddition, one column is constructed by n read blocks BKik arranged inthe Y-direction. The memory cell array 11 has j columns.

[0145] One terminal of each of the four TMR elements 12 in the blockBKik is commonly connected. The terminals are connected to a source lineSLi (i=1, 2, . . . , j) through a read select switch (block selectswitch or row select switch) RSW formed from, e.g., a MOS transistor.The source line SLi extends in the Y-direction. For example, one sourceline SLi is arranged in one column.

[0146] The source line SLi is connected to a ground point VSS through,e.g., a column select switch 29C formed from a MOS transistor.

[0147] In read operation, in the selected row, the read select switchesRSW in the read blocks BKik are turned on. In the selected column, thecolumn select switch 29C is turned on. For this reason, the potential ofthe source line SLi becomes the ground potential VSS. That is, a readcurrent flows only to the TMR elements 12 in the read block BKik locatedat the intersection between the selected row and the selected column.

[0148] In the read mode, in an unselected column, the column selectswitch 29C is OFF. Hence, the other terminal of each TMR element 12 inthe read blocks BKik in an unselected column is short-circuited.

[0149] In this case, if read bit lines BL4(j−1)+1, BL4(j−1)+2,BL4(j−1)+3 and BL4(j−1)+4 in an unselected column have differentpotentials, they may influence the read operation. To prevent this, theread bit lines BL4(j−1)+1, BL4(j−1)+2, BL4(j−1)+3 and BL4(j−1)+4 in anunselected column are set at an equipotential level (e.g., groundpotential).

[0150] In the read operation, the read select switches RSW in anunselected row are OFF. Hence, the other terminal of each TMR element 12in the read blocks BKik in an unselected row is also short-circuited.

[0151] The short circuit between the TMR elements 12 in the read blocksBKik belonging to the selected column and unselected rows may influencethe read operation of the TMR elements 12 in the selected read blockBKik belonging to the selected row and column.

[0152] Hence, for example, as shown in FIG. 3, block select switches BSWeach formed from a MOS transistor may be arranged in each read blockBKik. The read bit lines BL4(j−1)+1, BL4(j−1)+2, BL4(j−1)+3 andBL4(j−1)+4 may be electrically connected only to the TMR elements 12 inthe selected read block BKik belonging to the selected row and column.In addition, the read current may be supplied only to these TMRelements.

[0153] The other terminal of each of the four TMR elements 12 in theread block BKik is independently connected to a corresponding one of theread bit lines BL4(j−1)+1, BL4(j−1)+2, BL4(j−1)+3 and BL4(j−1)+4. Fourread bit lines BL4(j−1)+1, BL4(j−1)+2, BL4(j−1)+3 and BL4(j−1)+4 arearranged in one column in correspondence with four TMR elements 12 inone read block BKik.

[0154] The read bit lines BL4(j−1)+1, BL4(j−1)+2, BL4(j−1)+3 andBL4(j−1)+4 extend in the Y-direction. One end of each read bit line isconnected to a common data line 30 through the column select switch (MOStransistor) 29C. The common data line 30 is connected to a read circuit(including, e.g., a sense amplifier, selector, and output buffer) 29B.

[0155] A column select line signal CSLi (i=1, 2, . . . , j) is input tothe column select switch 29C. A column decoder 32 outputs the columnselect line signal CSLi.

[0156] In this example, the read bit lines BL4(j−1)+1, BL4(j−1)+2,BL4(j−1)+3 and BL4(j−1)+4 also function as write bit lines.

[0157] That is, one end of each of the write/read bit lines BL4(j−1)+1,BL4(j−1)+2, BL4(j−1)+3 and BL4(j−1)+4 is connected to a circuit block29A including a column decoder and write bit line driver/sinker. Theother end is connected to a circuit block 31 including a column decoderand write bit line driver/sinker.

[0158] In write operation, the circuit blocks 29A and 31 are set in anoperative state. A write current flows to the write/read bit linesBL4(j−1)+1, BL4(j−1)+2, BL4(j−1)+3 and BL4(j−1)+4 in accordance withwrite data in a direction toward the circuit block 29A or 31.

[0159] A plurality of (in this example, four) write word linesWWL4(n−1)+1, WWL4(n−1)+2, WWL4(n−1)+3 and WWL4(n−1)+4 that extend in theX-direction and are stacked in the Z-direction are arranged near thefour TMR elements 12 of the read block BKik. Here, n indicates a rownumber (n=1, 2, . . . )

[0160] In this example, as for the write word lines extending in theX-direction, one write word line is arranged at one stage in one row.That is, one write word line corresponds to one TMR element in theselected read block BKik. In this case, the number of write word linesin one row extending in the X-direction is the same as the number ofstages of the stacked TMR elements 12.

[0161] As shown in FIGS. 95 and 96, one write word line may be shared bya plurality of TMR elements (an upper TMR element and lower TMR element)in consideration of planarizing insulating films immediately under theTMR elements 12 or reducing the manufacturing cost.

[0162] The TMR element in the block and a detailed structure near itwill be described in detail in the section about the device structure.

[0163] One end of each of the write word lines WWL4(n−1)+1, WWL4(n−1)+2,WWL4(n−1)+3 and WWL4(n−1)+4 is connected to a write word line driver23A-n. The other end is connected to a write word line sinker 24-n.

[0164] The gate of the read select switch (MOS transistor) RSW isconnected to a read word line RWLn (n=1, 2, . . . ) One read word lineRWLn is arranged in one row, i.e., shared by the plurality of blocksBKik arranged in the X-direction.

[0165] For example, when one column has four blocks, the number of readword lines RWLn is four. Each read word line RWLn extends in theX-direction. One end of the read word line RWLn is connected to a readword line driver 23B-n.

[0166] When one read block BKik has a circuit structure shown in FIG. 3,the read word line RWLn is also connected to the gates of the blockselect switches BSW (MOS transistors).

[0167] That is, when the circuit structure shown in FIG. 3 is employed,only the read select switches RSW and block select switches BSW in theblocks BKik on the selected row, i.e., the row for which the potentialof the read word line RWLn is at “H” level, are turned on.

[0168] In the write operation, a row decoder 25-n selects one of theplurality of rows on the basis of row address signals. The write wordline driver 23A-n supplies write currents to the write word linesWWL4(n−1)+1, WWL4(n−1)+2, WWL4(n−1)+3 and WWL4(n−1)+4 in the selectedrow. The write currents are absorbed by the write word line sinker 24-n.

[0169] In the read operation, the row decoder 25-n selects one of theplurality of rows on the basis of row address signals. The read wordline driver 23B-n supplies a read voltage (=“H”) to the read word lineRWLn in the selected row.

[0170] In the magnetic random access memory of the present invention,one column is constructed by a plurality of read blocks. A plurality ofTMR elements in each read block are connected to different read bitlines, respectively. Hence, data of the plurality of TMR elements in theread block can be read at once by one read step.

[0171] The plurality of TMR elements in each read block are stacked toform a plurality of stages on a semiconductor substrate. Each read bitline also functions as a write bit line. That is, since nointerconnection that functions only as a write bit line need be formedin the cell array, the cell array structure can be simplified.

[0172] In each read block, the read select switch RSW and block selectswitches (FIG. 3) are arranged. A column select switch is connectedbetween a source line and the ground point. In the read operation, theTMR elements in an unselected read block do not influence the readoperation. Hence, the read operation stabilizes.

[0173] {circle over (2)} Device Structure

[0174] The device structure will be described next.

[0175]FIGS. 4 and 5 show the device structure of one block of themagnetic random access memory as Structural Example 1 of the presentinvention.

[0176]FIG. 4 shows the Y-direction section of one block of the magneticrandom access memory. FIG. 5 shows the X-direction section of one blockof the magnetic random access memory. The same reference numerals as inFIGS. 1 to 3 denote the same elements in FIGS. 4 and 5 to show thecorrespondence between the elements.

[0177] The read select switch (MOS transistor) RSW is arranged on thesurface region of a semiconductor substrate 41. The source of the readselect switch RSW is connected to the source line SLi through a contactplug 42F. The source line SLi extends straight, e.g., in the Y-directionand is connected to the ground supply through a column select switcharranged at the peripheral portion of the memory cell array region.

[0178] The gate of the read select switch (MOS transistor) RSW serves asthe read word line RWLn. The read word line RWLn extends in theX-direction. The four TMR elements (MTJ (Magnetic Tunnel Junction)elements) MTJ1, MTJ2, MTJ3 and MTJ4 are stacked at a plurality of stageson the read select switch RSW.

[0179] One end (in this example, the lower end) of each of the TMRelements MTJ1, MTJ2, MTJ3 and MTJ4 is connected to a corresponding oneof lower electrodes 44A, 44B, 44C and 44D. Contact plugs 42A, 42B, 42C,42D and 42E and intermediate layer 43 electrically connect the lowerelectrodes 44A, 44B, 44C and 44D to each other and also electricallyconnect them to the drain of the read select switch RSW.

[0180] The other end (in this example, the upper end) of each of the TMRelements MTJ1, MTJ2, MTJ3 and MTJ4 is electrically connected to acorresponding one of read/write bit lines BL1, BL2, BL3 and BL4. Theread/write bit lines BL1, BL2, BL3 and BL4 extend in the Y-direction.

[0181] The TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are independentlyconnected to the read/write bit lines BL1, BL2, BL3 and BL4,respectively. That is, four read/write bit lines BL1, BL2, BL3 and BL4are arranged in correspondence with four TMR elements MTJ1, MTJ2, MTJ3and MTJ4.

[0182] Write word lines WWL1, WWL2, WWL3 and WWL4 are arrangedimmediately under the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 and nearthem. The write word lines WWL1, WWL2, WWL3 and WWL4 extend in theX-direction.

[0183] In this example, four write word lines WWL1, WWL2, WWL3 and WWL4are arranged in correspondence with four TMR elements MTJ1, MTJ2, MTJ3and MTJ4.

[0184] In this example, the read/write bit lines BL1, BL2, BL3 and BL4extending in the Y-direction are arranged on the TMR elements MTJ1,MTJ2, MTJ3 and MTJ4. The write word lines WWL1, WWL2, WWL3 and WWL4extending in the X-direction are arranged below the TMR elements MTJ1,MTJ2, MTJ3 and MTJ4.

[0185] However, the positional relationship of the read/write bit linesBL1, BL2, BL3 and BL4 and write word lines WWL1, WWL2, WWL3 and WWL4with respect to the TMR elements is not limited to this.

[0186] For example, as shown in FIGS. 97 and 98, the read/write bitlines BL1, BL2, BL3 and BL4 extending in the Y-direction may be arrangedunder the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4. The write word linesWWL1, WWL2, WWL3 and WWL4 extending in the X-direction may be arrangedabove the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4.

[0187] As shown in FIGS. 99 and 100, one write word line may be sharedby a plurality of TMR elements (an upper TMR element and lower TMRelement) in consideration of planarizing insulating films right underthe TMR elements 12 or reducing the manufacturing cost.

[0188] According to such a device structure, the plurality of TMRelements MTJ1, MTJ2, MTJ3 and MTJ4 in the read block are connected tothe different read/write bit lines BL1, BL2, BL3 and BL4, respectively.Hence, data of the plurality of TMR elements MTJ1, MTJ2, MTJ3 and MTJ4in the read block can be read at once by one read step.

[0189] The plurality of TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 in theread block are stacked at a plurality of stages on the semiconductorsubstrate 41. In addition, only the read/write bit lines BL1, BL2, BL3and BL4 extend in the Y-direction. For this reason, even when the numberof stacked TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 is increased, the cellarray structure is not complicated.

[0190]FIG. 6 shows the positional relationship between the TMR elementsand the write word lines and read/write bit lines in the devicestructure shown in FIGS. 4 and 5.

[0191] In the device structure shown in FIGS. 4 and 5, the lowerelectrodes 44A, 44B, 44C and 44D, write word lines WWL1, WWL2, WWL3 andWWL4, and read/write bit lines BL1, BL2, BL3 and BL4 are arranged at therespective stages of the plurality of stacked TMR elements MTJ1, MTJ2,MTJ3 and MTJ4.

[0192] The layouts of, e.g., the stages of the TMR elements MTJ1, MTJ2,MTJ3 and MTJ4 are set to be identical.

[0193] Each of the lower electrodes 44A, 44B, 44C and 44D has, e.g., arectangular pattern. They have contact regions corresponding to thecontact plugs 42A to 42E at partial portions. The lower electrodes 44A,44B, 44C and 44D have the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 at theremaining portions.

[0194] The TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are arranged at theintersections between the write word lines WWL1, WWL2, WWL3 and WWL4 andthe read/write bit lines BL1, BL2, BL3 and BL4.

[0195] {circle over (3)} Structural Example of TMR Element

[0196] FIGS. 7 to 9 show structural examples of the TMR element.

[0197] The TMR element shown in FIG. 7 has the most basic structurehaving two ferromagnetic layers and a tunneling barrier layer sandwichedbetween these layers.

[0198] An anti-ferromagnetic layer for fixing the magnetizing directionis added to a fixed layer (pinning layer) of the two ferromagneticlayers, in which the magnetizing direction is fixed. The magnetizingdirection in a free layer (storing layer) of the two ferromagneticlayers, in which the magnetizing direction can be freely changed, isdetermined by a synthesized magnetic field formed by a write word lineand write bit line.

[0199] The TMR element shown in FIG. 8 has two tunneling barrier layersin it to make the bias voltage higher than in the TMR element shown inFIG. 7.

[0200] The TMR element shown in FIG. 8 can be regarded to have astructure (double junction structure) in which two TMR elements shown inFIG. 7 are connected in series.

[0201] In this example, the TMR element has three ferromagnetic layers.Tunneling barrier layers are inserted between the ferromagnetic layers.Antiferromagnetic layers are added to the two ferromagnetic layers(pinning layers) at two ends. The middle layer in the threeferromagnetic layers serves as a free layer (storing layer) in which themagnetizing direction can be freely changed.

[0202] The TMR element shown in FIG. 9 can easily close lines ofmagnetic force in the ferromagnetic layer serving as a storing layer, ascompared to the TMR element shown in FIG. 7.

[0203] For the TMR element of this example, it can be regarded that thestoring layer of the TMR element shown in FIG. 7 is replaced with astoring layer formed from two ferromagnetic layers and a nonmagneticmetal layer (e.g., an aluminum layer) sandwiched between those layers.

[0204] When the storing layer of the TMR element has a three-layeredstructure made of two ferromagnetic layers and a nonmagnetic metal layersandwiched between these layers, lines of magnetic force in the twoferromagnetic layers of the storing layer readily close. That is, sinceany anti-magnetic field component in the two ferromagnetic layers of thestoring layer can be prevented, the MR ratio can be improved.

[0205] The structural examples of the TMR element have been describedabove. In the present invention (circuit structure, device structure,read operation mechanism, read circuit, and manufacturing method), thestructure of the TMR element is not particularly limited. Theabove-described three structural examples are mere representativeexamples of the TMR element structure.

(2) STRUCTURAL EXAMPLE 2

[0206] Structural Example 2 is a modification to Structural Example 1. Acharacteristic feature of Structural Example 2, which is different fromStructural Example 1, is the direction of a read select switch. That is,in Structural Example 2, the read select switch of Structural Example 1is rotated by 90°.

[0207] {circle over (1)} Circuit Structure

[0208] The circuit structure will be described first.

[0209]FIG. 10 shows main part of a magnetic random access memory asStructural Example 2 of the present invention. The circuit diagram ofFIG. 10 corresponds to that of FIG. 2. The outline of the memory cellarray and its peripheral portion in Structural Example 2 is the same asin FIG. 1.

[0210] One terminal of each of four TMR elements MTJ1, MTJ2, MTJ3 andMTJ4 in a block BK11 is connected to a source line SL1 through a readselect switch (block select switch or row select switch) RSW formedfrom, e.g., a MOS transistor.

[0211] The line that connects the source and drain of the read selectswitch RSW is parallel to the X-direction. That is, the channel lengthof the read select switch RSW is the X-direction length of the channelof the read select switch RSW. The channel width is the Y-directionwidth of the channel of the read select switch RSW.

[0212] The gate of the read select switch RSW extends in the Y-directionand is connected, at a predetermined portion, to a read word line RWL1that extends in the X-direction.

[0213] The source line SL1 extends in the Y-direction. For example, onesource line is arranged in one column. The source line SL1 is connectedto the ground supply through a column select switch 29C formed from,e.g., a MOS transistor.

[0214] Assume that the read block BK11 is selected in read operation. Atthis time, the read select switch RSW in the read block BK11 is turnedon. In addition, the column select switch 29C is turned on. For thisreason, the potential of the source line SL1 changes to the groundpotential. That is, a read current flows to the TMR elements MTJ1, MTJ2,MTJ3 and MTJ4 in the read block BK11.

[0215] The other terminal of each of the four TMR elements MTJ1, MTJ2,MTJ3 and MTJ4 in the read block BK11 is independently connected to acorresponding one of read bit lines BL1, BL2, BL3 and BL4. That is, fourread bit lines BL1, BL2, BL3 and BL4 are arranged in correspondence withthe four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 in the read block BK11.

[0216] The read bit lines BL1, BL2, BL3 and BL4 extend in theY-direction. One end of each read bit line is connected to a common dataline 30 through the column select switch (MOS transistor) 29C. Thecommon data line 30 is connected to a read circuit (including, e.g., asense amplifier, selector and output buffer) 29B.

[0217] A column select line signal CSL1 is input to the column selectswitch 29C. A column decoder 32 outputs the column select line signalCSL1.

[0218] In this example, the read bit lines BL1, BL2, BL3 and BL4 alsofunction as write bit lines.

[0219] That is, one end of each of the read/write bit lines BL1, BL2,BL3 and BL4 is connected to a circuit block 29A including a columndecoder and write bit line driver/sinker. The other end is connected toa circuit block 31 including a column decoder and write bit linedriver/sinker.

[0220] In write operation, the circuit blocks 29A and 31 are set in anoperative state. A write current flows to the read/write bit lines BL1,BL2, BL3 and BL4 in accordance with write data in a direction toward thecircuit block 29A or 31.

[0221] A plurality of (in this example, four) write word lines WWL1,WWL2, WWL3 and WWL4 that extend in the X-direction and are stacked inthe Z-direction are arranged near the four TMR elements MTJ1, MTJ2, MTJ3and MTJ4 of the read block BK11.

[0222] In this example, as for the write word lines extending in theX-direction, one write word line is arranged at one stage in one row.That is, one write word line corresponds to one TMR element in the readblock BK11. In this case, the number of write word lines in one rowextending in the X-direction is the same as the number of stages of thestacked TMR elements MTJ1, MTJ2, MTJ3 and MTJ4.

[0223] As shown in FIG. 101, one write word line may be shared by aplurality of TMR elements (an upper TMR element and lower TMR element)in consideration of planarizing insulating films immediately under theTMR elements MTJ1, MTJ2, MTJ3 and MTJ4 or reducing the manufacturingcost.

[0224] One end of each of the write word lines WWL1, WWL2, WWL3 and WWL4is connected to a write word line driver 23A-n. The other end isconnected to a write word line sinker 24-n.

[0225] The gate of the read select switch (MOS transistor) RSW isconnected to the read word line RWL1. One read word line RWL1 isarranged in one row, i.e., shared by the plurality of blocks arranged inthe X-direction.

[0226] In the write operation, a row decoder 25-1 selects one of theplurality of rows on the basis of row address signals. The write wordline driver 23A-n supplies write currents to the write word lines WWL1,WWL2, WWL3 and WWL4 in the selected row. The write currents are absorbedby the write word line sinker.

[0227] In the read operation, the row decoder 25-1 selects one of theplurality of rows on the basis of row address signals. A read word linedriver 23B-1 supplies a read voltage (=“H”) to the read word line RWL1in the selected row.

[0228] In the magnetic random access memory of the present invention,one column is constructed by a plurality of read blocks. A plurality ofTMR elements in each read block are connected to different read bitlines, respectively. Hence, data of the plurality of TMR elements in theread block can be read at once by one read step.

[0229] The plurality of TMR elements in each read block are stacked toform a plurality of stages on a semiconductor substrate. Each read bitline also functions as a write bit line. That is, since nointerconnection that functions only as a write bit line need be formedin the cell array, the cell array structure can be simplified.

[0230] In each read block, the read select switch RSW is arranged. Acolumn select switch is connected between a source line and the groundline. In the read operation, the TMR elements in an unselected readblock rarely influence the read operation. Hence, the read operationstabilizes.

[0231] {circle over (2)} Device Structure

[0232] The device structure will be described next.

[0233]FIGS. 11 and 12 show the device structure of one block of themagnetic random access memory as Structural Example 2 of the presentinvention.

[0234]FIG. 11 shows the Y-direction section of one block of the magneticrandom access memory. FIG. 12 shows the X-direction section of one blockof the magnetic random access memory. The same reference numerals as inFIG. 9 denote the same elements in FIGS. 11 and 12 to show thecorrespondence between the elements.

[0235] The read select switch (MOS transistor) RSW is arranged on thesurface region of a semiconductor substrate 41. The source of the readselect switch RSW is connected to the source line SLi through a contactplug 42F. The source line SLi extends straight, e.g., in the Y-directionand is connected to the ground supply through a column select switcharranged at the peripheral portion of the memory cell array region.

[0236] The gate of the read select switch (MOS transistor) RSW serves asthe read word line RWLn. The read word line RWLn extends in theX-direction. The four TMR elements (MTJ (Magnetic Tunnel Junction)elements) MTJ1, MTJ2, MTJ3 and MTJ4 are stacked at a plurality of stageson the read select switch RSW.

[0237] One end (in this example, the lower end) of each of the TMRelements MTJ1, MTJ2, MTJ3 and MTJ4 is connected to a corresponding oneof lower electrodes 44A, 44B, 44C and 44D. Contact plugs 42A, 42B, 42C,42D and 42E and intermediate layer 43 electrically connect the lowerelectrodes 44A, 44B, 44C and 44D to each other and also electricallyconnect them to the drain of the read select switch RSW.

[0238] The other end (in this example, the upper end) of each of the TMRelements MTJ1, MTJ2, MTJ3 and MTJ4 is electrically connected to acorresponding one of the read/write bit lines BL1, BL2, BL3 and BL4. Theread/write bit lines BL1, BL2, BL3 and BL4 extend in the Y-direction.

[0239] The TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are independentlyconnected to the read/write bit lines BL1, BL2, BL3 and BL4,respectively. That is, four read/write bit lines BL1, BL2, BL3 and BL4are arranged in correspondence with four TMR elements MTJ1, MTJ2, MTJ3and MTJ4.

[0240] The write word lines WWL1, WWL2, WWL3 and WWL4 are arranged rightunder the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 and near them. Thewrite word lines WWL1, WWL2, WWL3 and WWL4 extend in the X-direction.

[0241] In this example, four write word lines WWL1, WWL2, WWL3 and WWL4are arranged in correspondence with four TMR elements MTJ1, MTJ2, MTJ3and MTJ4.

[0242] In this example, the read/write bit lines BL1, BL2, BL3 and BL4extending in the Y-direction are arranged on the TMR elements MTJ1,MTJ2, MTJ3 and MTJ4. The write word lines WWL1, WWL2, WWL3 and WWL4extending in the X-direction are arranged below the TMR elements MTJ1,MTJ2, MTJ3 and MTJ4.

[0243] However, the positional relationship of the read/write bit linesBL1, BL2, BL3 and BL4 and write word lines WWL1, WWL2, WWL3 and WWL4with respect to the TMR elements is not limited to this.

[0244] For example, as shown in FIGS. 102 and 103, the read/write bitlines BL1, BL2, BL3 and BL4 extending in the Y-direction may be arrangedunder the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4. The write word linesWWL1, WWL2, WWL3 and WWL4 extending in the X-direction may be arrangedabove the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4.

[0245] As shown in FIGS. 104 and 105, one write word line may be sharedby a plurality of TMR elements (an upper TMR element and lower TMRelement) in consideration of planarizing insulating films immediatelyunder the TMR elements 12 or reducing the manufacturing cost.

[0246] According to such a device structure, the plurality of TMRelements MTJ1, MTJ2, MTJ3 and MTJ4 in the read block are connected tothe different read/write bit lines BL1, BL2, BL3 and BL4, respectively.Hence, data of the plurality of TMR elements MTJ1, MTJ2, MTJ3 and MTJ4in the read block can be read at once by one read step.

[0247] The plurality of TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 in theread block are stacked at a plurality of stages on the semiconductorsubstrate 41. In addition, only the read/write bit lines BL1, BL2, BL3and BL4 extend in the Y-direction. For this reason, even when the numberof stacked TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 is increased, the cellarray structure is not complicated.

(3) STRUCTURAL EXAMPLE 3

[0248] Structural Example 3 is a modification to Structural Example 1. Acharacteristic feature of Structural Example 3, which is different fromStructural Example 1, is the interconnection connected to the gate andsource of a read select switch.

[0249] That is, in Structural Example 3, the gate of the read selectswitch is connected to a decode line, and its source is connected to aread word line. The read select switch in a read block is selected bycolumn address signals.

[0250] {circle over (1)} Circuit Structure

[0251] The circuit structure will be described first.

[0252]FIG. 13 shows main part of a magnetic random access memory asStructural Example 3 of the present invention. FIG. 14 shows an exampleof a column select switch shown in FIG. 13.

[0253] A memory cell array 11 has a plurality of TMR elements 12 arrayedin the X-, Y- and Z-directions. The Z-direction means a directionperpendicular to the X- and Y-directions, i.e., a directionperpendicular to the memory cell array plane.

[0254] The memory cell array 11 has a cell array structure formed from jTMR elements 12 arranged in the X-direction, n TMR elements 12 arrangedin the Y-direction, and four TMR elements 12 stacked in the Z-direction.The number of TMR elements 12 stacked in the Z-direction is four.However, the number of TMR elements is not particularly limited as longas the number is two or more.

[0255] The four TMR elements 12 stacked in the Z-direction construct oneread block BKik (i=1, 2, . . . , j, k=1, 2, . . . , n). In fact, thefour TMR elements 12 in the read block BKik overlap one another in thedirection (Z-direction) perpendicular to the memory cell array plane.

[0256] In this example, one row is constructed by j read blocks BKikarranged in the X-direction. The memory cell array 11 has n rows. Inaddition, one column is constructed by n read blocks BKik arranged inthe Y-direction. The memory cell array 11 has j columns.

[0257] One terminal of each of the four TMR elements 12 in the blockBKik is connected to a read word line RWLn (n=1, 2, . . . ) through aread select switch (block select switch or row select switch) RSW formedfrom, e.g., a MOS transistor. The read word line RWLn extends in theX-direction. For example, one read word line RWLn is arranged in onerow.

[0258] The gate of the read select switch RSW is connected to a decodeline DLi (i=1, 2, . . . ) The decode line DLi extends in theY-direction. For example, one decode line is arranged in one column. Oneend of the decode line DLi is connected to a column decoder 32.

[0259] In this example, the decode line DLi is connected to the columndecoder 32. That is, a column select switch and read select switches inread blocks, which are present on a single column, execute the sameoperation.

[0260] For example, when the column decoder 32 sets a column selectsignal CSL1 at “H” level, the column select switch of the column towhich the read blocks BK11, . . . , BK1 n belong is turned on. At thesame time, the read select switches RSW in the read blocks BK11, . . . ,BK1 n are turned on.

[0261] In this example, both a column select switch 29C and the readselect switch RSW in the read block BKik are controlled using a columnselect signal CSLi (i=1, 2, . . . ) output from the column decoder 32.

[0262] Instead, for example, as shown in FIG. 15, the column selectswitch 29C and the read select switch RSW in the read block BKik may becontrolled by different signals.

[0263] That is, in the example shown in FIG. 15, the column selectswitch 29C is controlled by the column select signal CSL1 output from acolumn decoder 32A. The read select switch RSW in the read block BK11 iscontrolled by a block select signal BSL1 output from a column decoder32B.

[0264] The column decoders 32A and 32B have identical structures, aswill be described in the section about the read circuit.

[0265] In read operation, in the selected row, the potential of the readword line RWLn changes to “L” level. In the selected column, the readselect switches RSW in the read blocks BKik are turned on, as describedabove.

[0266] Hence, a read current flows only to the TMR elements 12 in theread block BKik located at the intersection between the selected row andthe selected column.

[0267] In the read mode, in an unselected column, the read selectswitches RSW in the read blocks BKik are OFF. Hence, the other terminalof each TMR element 12 in the read blocks BKik in an unselected columnis short-circuited.

[0268] In this case, if read bit lines BL4(j−1)+1, BL4(j−1)+2,BL4(j−1)+3 and BL4(j−1)+4 in an unselected column have differentpotentials, they may influence the read operation. To prevent this, theread bit lines BL4(j−1)+1, BL4(j−1)+2, BL4(j−1)+3 and BL4(j−1)+4 in anunselected column are set at an equipotential level (e.g., groundpotential).

[0269] In the read operation, in the selected column and unselectedrows, for example, the read word lines RWLn are set in the floatingstate (fixed potential; it may be the same potential as that of theselected bit line). In this case, in the selected column and unselectedrows, since the read select switches RSW in the read blocks BKik are ON,the other terminal of each TMR element 12 in the blocks BKik isshort-circuited.

[0270] The short circuit between the TMR elements 12 in the read blocksBKik belonging to the selected column and unselected rows may influencethe read operation of the TMR elements 12 in the selected read blockBKik belonging to the selected row and column.

[0271] Hence, for example, as shown in FIG. 16, block select switchesBSW each formed from a MOS transistor may be arranged in each read blockBKik. The read bit lines BL4(j−1)+1, BL4(j−1)+2, BL4(j−1)+3 andBL4(j−1)+4 may be electrically connected only to the TMR elements 12 inthe selected read block BKik belonging to the selected row and column.In addition, the read current may be supplied only to these TMRelements.

[0272] The other terminal of each of the four TMR elements 12 in theread block BKik is independently connected to a corresponding one of theread bit lines BL4(j−1)+1, BL4(j−1)+2, BL4(j−1)+3 and BL4(j−1)+4. Fourread bit lines BL4(j−1)+1, BL4(j−1)+2, BL4(j−1)+3 and BL4(j−1)+4 arearranged in one column in correspondence with four TMR elements 12 inone read block BKik.

[0273] The read bit lines BL4(j−1)+1, BL4(j−1)+2, BL4(j−1)+3 andBL4(j−1)+4 extend in the Y-direction. One end of each read bit line isconnected to a common data line 30 through the column select switch (MOStransistor) 29C. The common data line 30 is connected to a read circuit(including, e.g., a sense amplifier, selector and output buffer) 29B.

[0274] A column select line signal CSLi (i=1, 2, . . . , j) is input tothe column select switch 29C. The column decoder 32 outputs the columnselect line signal CSLi.

[0275] In this example, the read bit lines BL4(j−1)+1, BL4(j−1)+2,BL4(j−1)+3 and BL4(j−1)+4 also function as write bit lines.

[0276] That is, one end of each of the write/read bit lines BL4(j−1)+1,BL4(j−1)+2, BL4(j−1)+3 and BL4(j−1)+4 is connected to a circuit block29A including a column decoder and write bit line driver/sinker. Theother end is connected to a circuit block 31 including a column decoderand write bit line driver/sinker.

[0277] In write operation, the circuit blocks 29A and 31 are set in anoperative state. A write current flows to the write/read bit linesBL4(j−1)+1, BL4(j−1)+2, BL4(j−1)+3 and BL4(j−1)+4 in accordance withwrite data in a direction toward the circuit block 29A or 31.

[0278] A plurality of (in this example, four) write word linesWWL4(n−1)+1, WWL4(n−1)+2, WWL4(n−1)+3 and WWL4(n−1)+4 that extend in theX-direction and are stacked in the Z-direction are arranged near thefour TMR elements 12 of the read block BKik. Here, n indicates a rownumber (n=1, 2, . . . )

[0279] In this example, as for the write word lines extending in theX-direction, one write word line is arranged at one stage in one row.That is, one write word line corresponds to one TMR element in theselected read block BKik. In this case, the number of write word linesin one row extending in the X-direction is the same as the number ofstages of the stacked TMR elements 12.

[0280] As shown in FIGS. 106 and 107, one write word line may be sharedby a plurality of TMR elements (an upper TMR element and lower TMRelement) in consideration of planarizing insulating films right underthe TMR elements 12 or reducing the manufacturing cost.

[0281] The TMR element in the block and a detailed structure near itwill be described in detail in the section about the device structure.

[0282] One end of each of the write word lines WWL4(n−1)+1, WWL4(n−1)+2,WWL4(n−1)+3 and WWL4(n−1)+4 is connected to a write word line driver23A-n. The other end is connected to a write word line sinker 24-n.

[0283] The source of the read select switch (MOS transistor) RSW isconnected to the read word line RWLn (n=1, 2, . . . ) One read word lineRWLn is arranged in one row, i.e., shared by the plurality of blocksBKik arranged in the X-direction.

[0284] When one read block BKik has a circuit structure shown in FIG.16, the read word line RWLn is also connected to the gates of the blockselect switches BSW (MOS transistors) through, e.g., an inverter.

[0285] That is, when the circuit structure shown in FIG. 16 is employed,the block select switches BSW in the blocks BKik on the selected row,i.e., the row for which the potential of the read word line RWLn is at“L” level, are turned on.

[0286] The potential of the read word line RWLn of the selected rowchanges to “L” level. In addition, the read select switches RSW in theread blocks BKik of the selected column are turned on. For this reason,the read bit lines BL4(j−1)+1, BL4(j−1)+2, BL4(j−1)+3 and BL4(j−1)+4 areelectrically connected only to the TMR elements 12 in the selected readblock BKik belonging to the selected row and column. In addition, theread current flows only to these TMR elements.

[0287] In the write operation, a row decoder 25-n selects one of theplurality of rows on the basis of row address signals. The write wordline driver 23A-n supplies write currents to the write word linesWWL4(n−1)+1, WWL4(n−1)+2, WWL4(n−1)+3 and WWL4(n−1)+4 in the selectedrow. The write currents are absorbed by the write word line sinker 24-n.

[0288] In the read operation, the row decoder 25-n selects one of theplurality of rows on the basis of row address signals. The read wordline driver 23B-n supplies a read voltage (=“L”) to the read word lineRWLn in the selected row.

[0289] In the magnetic random access memory of the present invention,one column is constructed by a plurality of read blocks. A plurality ofTMR elements in each read block are connected to different read bitlines, respectively. Hence, data of the plurality of TMR elements in theread block can be read at once by one read step.

[0290] The plurality of TMR elements in each read block are stacked toform a plurality of stages on a semiconductor substrate. Each read bitline also functions as a write bit line. That is, since nointerconnection that functions only as a write bit line need be formedin the cell array, the cell array structure can be simplified.

[0291] In each read block, the read select switch RSW and block selectswitches (FIG. 16) are arranged. The read select switch is controlled bythe output signal from the column decoder. The block select switch iscontrolled by the output from the row decoder. Hence, in the readoperation, the TMR elements in an unselected read block do not influencethe read operation. For this reason, the read operation stabilizes.

[0292] {circle over (2)} Device Structure

[0293] The device structure will be described next.

[0294]FIGS. 17 and 18 show the device structure of one block of themagnetic random access memory as Structural Example 3 of the presentinvention.

[0295]FIG. 17 shows the Y-direction section of one block of the magneticrandom access memory. FIG. 18 shows the X-direction section of one blockof the magnetic random access memory. The same reference numerals as inFIGS. 13 to 16 denote the same elements in FIGS. 17 and 18 to show thecorrespondence between the elements.

[0296] The read select switch (MOS transistor) RSW is arranged on thesurface region of a semiconductor substrate 41. The source of the readselect switch RSW is connected to the read word line RWLn through acontact plug 42F. The read word line RWLn extends straight, e.g., in theX-direction and is connected to the read word line driver arranged atthe peripheral portion of the memory cell array region.

[0297] The gate of the read select switch (MOS transistor) RSW serves asa decode line DLj. The decode line DLj extends in the Y-direction at aportion other than the sections shown in FIGS. 17 and 18. The four TMRelements (MTJ (Magnetic Tunnel Junction) elements) MTJ1, MTJ2, MTJ3 andMTJ4 are stacked at a plurality of stages on the read select switch RSW.

[0298] One end (in this example, the lower end) of each of the TMRelements MTJ1, MTJ2, MTJ3 and MTJ4 is connected to a corresponding oneof lower electrodes 44A, 44B, 44C and 44D. Contact plugs 42A, 42B, 42C,42D and 42E and intermediate layer 43 electrically connect the lowerelectrodes 44A, 44B, 44C and 44D to each other and also electricallyconnect them to the drain of the read select switch RSW.

[0299] The other end (in this example, the upper end) of each of the TMRelements MTJ1, MTJ2, MTJ3 and MTJ4 is electrically connected to acorresponding one of read/write bit lines BL1, BL2, BL3 and BL4. Theread/write bit lines BL1, BL2, BL3 and BL4 extend in the Y-direction.

[0300] The TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are independentlyconnected to the read/write bit lines BL1, BL2, BL3 and BL4,respectively. That is, four read/write bit lines BL1, BL2, BL3 and BL4are arranged in correspondence with four TMR elements MTJ1, MTJ2, MTJ3and MTJ4.

[0301] Write word lines WWL1, WWL2, WWL3 and WWL4 are arrangedimmediately under the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 and nearthem. The write word lines WWL1, WWL2, WWL3 and WWL4 extend in theX-direction.

[0302] In this example, four write word lines WWL1, WWL2, WWL3 and WWL4are arranged in correspondence with four TMR elements MTJ1, MTJ2, MTJ3and MTJ4.

[0303] In this example, the read/write bit lines BL1, BL2, BL3 and BL4extending in the Y-direction are arranged on the TMR elements. The writeword lines WWL1, WWL2, WWL3 and WWL4 extending in the X-direction arearranged below the TMR elements. However, the positional relationship ofthe read/write bit lines BL1, BL2, BL3 and BL4 and write word linesWWL1, WWL2, WWL3 and WWL4 with respect to the TMR elements is notlimited to this.

[0304] For example, as shown in FIGS. 108 and 109, the read/write bitlines BL1, BL2, BL3 and BL4 extending in the Y-direction may be arrangedunder the TMR elements.

[0305] The write word lines WWL1, WWL2, WWL3 and WWL4 extending in theX-direction may be arranged above the TMR elements.

[0306] As shown in FIGS. 110 and 111, one write word line may be sharedby a plurality of TMR elements (an upper TMR element and lower TMRelement) in consideration of planarizing insulating films immediatelyunder the TMR elements 12 or reducing the manufacturing cost. Accordingto such a device structure, the plurality of TMR elements MTJ1, MTJ2,MTJ3 and MTJ4 in the read block are connected to the differentread/write bit lines BL1, BL2, BL3 and BL4, respectively. Hence, data ofthe plurality of TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 in the readblock can be read at once by one read step.

[0307] The plurality of TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 in theread block are stacked at a plurality of stages on the semiconductorsubstrate 41. In addition, only the read/write bit lines BL1, BL2, BL3and BL4 extend in the Y-direction. For this reason, even when the numberof stacked TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 is increased, the cellarray structure is not complicated.

[0308]FIG. 19 shows the positional relationship between the TMR elementsand the write word lines and read/write bit lines in the devicestructure shown in FIGS. 17 and 18.

[0309] In the device structure shown in FIGS. 17 and 18, the lowerelectrodes 44A, 44B, 44C and 44D, write word lines WWL1, WWL2, WWL3 andWWL4, and read/write bit lines BL1, BL2, BL3 and BL4 are arranged at therespective stages of the plurality of stacked TMR elements MTJ1, MTJ2,MTJ3 and MTJ4.

[0310] The layouts of, e.g., the stages of the TMR elements MTJ1, MTJ2,MTJ3 and MTJ4 are set to be identical.

[0311] The lower electrodes 44A, 44B, 44C and 44D have, e.g., arectangular pattern. They have contact regions corresponding to thecontact plugs 42A to 42E at partial portions. The lower electrodes 44A,44B, 44C and 44D have the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 at theremaining portions.

[0312] The TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are arranged at theintersections between the write word lines WWL1, WWL2, WWL3 and WWL4 andthe read/write bit lines BL1, BL2, BL3 and BL4.

(4) STRUCTURAL EXAMPLE 4

[0313] Structural Example 4 is a modification to

[0314] Structural Example 3. A characteristic feature of StructuralExample 4, which is different from Structural Example 3, is thedirection of a read select switch. That is, in Structural Example 4, theread select switch of Structural Example 3 is rotated by 90°.

[0315] {circle over (1)} Circuit Structure

[0316] The circuit structure will be described first.

[0317]FIG. 20 shows main part of a magnetic random access memory asStructural Example 4 of the present invention. The circuit diagram ofFIG. 20 corresponds to that of FIG. 14. The outline of the memory cellarray and its peripheral portion in Structural Example 4 is the same asin FIG. 13.

[0318] One terminal of each of four TMR elements MTJ1, MTJ2, MTJ3 andMTJ4 in a block BK11 is connected to a read word line RWL1 through aread select switch (block select switch or row select switch) RSW formedfrom, e.g., a MOS transistor. The read word line RWL1 extends in theX-direction.

[0319] The line that connects the source and drain of the read selectswitch RSW is parallel to the X-direction. That is, the channel lengthof the read select switch RSW is the X-direction length of the channelof the read select switch RSW. The channel width is the Y-directionwidth of the channel of the read select switch RSW.

[0320] The gate of the read select switch RSW is connected to a decodeline DL1. The decode line DL1 extends in the Y-direction. The decodeline DL1 is connected to a column decoder 32. That is, the read selectswitch RSW is controlled by a decode signal CSL1 obtained by decoding acolumn address signal.

[0321] Assume that the read block BK11 is selected in read operation. Atthis time, since CSL1 changes to “H”, the read select switch RSW in theread block BK11 is turned on. In addition, the read word line RWL1changes to “L (ground potential VSS)”. Furthermore, a column selectswitch 29C is turned on.

[0322] Hence, a read current flows to the TMR elements MTJ1, MTJ2, MTJ3and MTJ4 in the read block BK11.

[0323] The other terminal of each of the four TMR elements MTJ1, MTJ2,MTJ3 and MTJ4 in the read block BK11 is independently connected to acorresponding one of read bit lines BL1, BL2, BL3 and BL4. That is, fourread bit lines BL1, BL2, BL3 and BL4 are arranged in correspondence withthe four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 in the read block BK11.

[0324] The read bit lines BL1, BL2, BL3 and BL4 extend in theY-direction. One end of each read bit line is connected to a common dataline 30 through the column select switch (MOS transistor) 29C. Thecommon data line 30 is connected to a read circuit (including, e.g., asense amplifier, selector and output buffer) 29B.

[0325] A column select line signal CSL1 is input to the column selectswitch 29C. The column decoder 32 outputs the column select line signalCSL1.

[0326] In this example, the read bit lines BL1, BL2, BL3 and BL4 alsofunction as write bit lines.

[0327] That is, one end of each of the read/write bit lines BL1, BL2,BL3 and BL4 is connected to a circuit block 29A including a columndecoder and write bit line driver/sinker. The other end is connected toa circuit block 31 including a column decoder and write bit linedriver/sinker.

[0328] In write operation, the circuit blocks 29A and 31 are set in anoperative state. A write current flows to the read/write bit lines BL1,BL2, BL3 and BL4 in accordance with write data in a direction toward thecircuit block 29A or 31.

[0329] A plurality of (in this example, four) write word lines WWL1,WWL2, WWL3 and WWL4 that extend in the X-direction and are stacked inthe Z-direction are arranged near the four TMR elements MTJ1, MTJ2, MTJ3and MTJ4 of the read block BK11.

[0330] In this example, as for the write word lines extending in theX-direction, one write word line is arranged at one stage in one row.That is, one write word line corresponds to one TMR element in the readblock BK11. In this case, the number of write word lines in one rowextending in the X-direction is the same as the number of stages of thestacked TMR elements MTJ1, MTJ2, MTJ3 and MTJ4.

[0331] As shown in FIG. 112, one write word line may be shared by aplurality of TMR elements (an upper TMR element and lower TMR element)in consideration of planarizing insulating films right under the TMRelements MTJ1, MTJ2, MTJ3 and MTJ4 or reducing the manufacturing cost.

[0332] One end of each of the write word lines WWL1, WWL2, WWL3 and WWL4is connected to a write word line driver 23A-n. The other end isconnected to a write word line sinker 24-n.

[0333] The gate of the read select switch (MOS transistor) RSW isconnected to the read word line RWL1. One read word line RWL1 isarranged in one row, i.e., shared by the plurality of blocks arranged inthe X-direction.

[0334] In the write operation, a row decoder 25-1 selects one of theplurality of rows on the basis of row address signals. The write wordline driver 23A-n supplies write currents to the write word lines WWL1,WWL2, WWL3 and WWL4 in the selected row. The write currents are absorbedby the write word line sinker.

[0335] In the read operation, the row decoder 25-1 selects one of theplurality of rows on the basis of row address signals. A read word linedriver 23B-1 supplies a read voltage (=“μL”) to the read word line RWL1in the selected row.

[0336] In the magnetic random access memory of the present invention,one column is constructed by a plurality of read blocks. A plurality ofTMR elements in each read block are connected to different read bitlines, respectively. Hence, data of the plurality of TMR elements in theread block can be read at once by one read step.

[0337] The plurality of TMR elements in each read block are stacked toform a plurality of stages on a semiconductor substrate. Each read bitline also functions as a write bit line. That is, since nointerconnection that functions only as a write bit line need be formedin the cell array, the cell array structure can be simplified.

[0338] In each read block, the read select switch RSW is arranged. Theread select switch RSW is controlled by the decode signal CSL1 obtainedby decoding a column address signal. The source of the read selectswitch RSW is connected to the read word line. Hence, the read operationcan be stably done with the simple arrangement.

[0339] {circle over (2)} Device Structure

[0340] The device structure will be described next.

[0341]FIGS. 21 and 22 show the device structure of one block of themagnetic random access memory as Structural Example 4 of the presentinvention.

[0342]FIG. 21 shows the Y-direction section of one block of the magneticrandom access memory. FIG. 22 shows the X-direction section of one blockof the magnetic random access memory. The same reference numerals as inFIG. 20 denote the same elements in FIGS. 21 and 22 to show thecorrespondence between the elements.

[0343] The read select switch (MOS transistor) RSW is arranged on thesurface region of a semiconductor substrate 41. The source of the readselect switch RSW is connected to the read word line RWLn through acontact plug 42F. The read word line RWLn extends, e.g., in theX-direction and is connected to the read word line driver arranged atthe peripheral portion of the memory cell array region.

[0344] The gate of the read select switch (MOS transistor) RSW serves asa decode line DLj. The decode line DLj extends in the Y-direction. Thedecode line DLj is connected to the column decoder arranged at theperipheral portion of the memory cell array region. The four TMRelements (MTJ (Magnetic Tunnel Junction) elements) MTJ1, MTJ2, MTJ3 andMTJ4 are stacked at a plurality of stages on the read select switch RSW.

[0345] One end (in this example, the lower end) of each of the TMRelements MTJ1, MTJ2, MTJ3 and MTJ4 is connected to a corresponding oneof lower electrodes 44A, 44B, 44C and 44D. Contact plugs 42A, 42B, 42C,42D and 42E and intermediate layer 43 electrically connect the lowerelectrodes 44A, 44B, 44C and 44D to each other and also electricallyconnect them to the drain of the read select switch RSW.

[0346] The other end (in this example, the upper end) of each of the TMRelements MTJ1, MTJ2, MTJ3 and MTJ4 is electrically connected to acorresponding one of the read/write bit lines BL1, BL2, BL3 and BL4. Theread/write bit lines BL1, BL2, BL3 and BL4 extend in the Y-direction.

[0347] The TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are independentlyconnected to the read/write bit lines BL1, BL2, BL3 and BL4,respectively. That is, four read/write bit lines BL1, BL2, BL3 and BL4are arranged in correspondence with four TMR elements MTJ1, MTJ2, MTJ3and MTJ4.

[0348] The write word lines WWL1, WWL2, WWL3 and WWL4 are arrangedimmediately under the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 and nearthem. The write word lines WWL1, WWL2, WWL3 and WWL4 extend in theX-direction.

[0349] In this example, four write word lines WWL1, WWL2, WWL3 and WWL4are arranged in correspondence with four TMR elements MTJ1, MTJ2, MTJ3and MTJ4.

[0350] In this example, the read/write bit lines BL1, BL2, BL3 and BL4extending in the Y-direction are arranged on the TMR elements. The writeword lines WWL1, WWL2, WWL3 and WWL4 extending in the X-direction arearranged below the TMR elements.

[0351] However, the positional relationship of the read/write bit linesBL1, BL2, BL3 and BL4 and write word lines WWL1, WWL2, WWL3 and WWL4with respect to the TMR elements is not limited to this.

[0352] For example, as shown in FIGS. 113 and 114, the read/write bitlines BL1, BL2, BL3 and BL4 extending in the Y-direction may be arrangedunder the TMR elements. The write word lines WWL1, WWL2, WWL3 and WWL4extending in the X-direction may be arranged above the TMR elements.

[0353] As shown in FIGS. 115 and 116, one write word line may be sharedby a plurality of TMR elements (an upper TMR element and lower TMRelement) in consideration of planarizing insulating films right underthe TMR elements 12 or reducing the manufacturing cost.

[0354] According to such a device structure, the plurality of TMRelements MTJ1, MTJ2, MTJ3 and MTJ4 in the read block are connected tothe different read/write bit lines BL1, BL2, BL3 and BL4, respectively.Hence, data of the plurality of TMR elements MTJ1, MTJ2, MTJ3 and MTJ4in the read block can be read at once by one read step.

[0355] The plurality of TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 in theread block are stacked at a plurality of stages on the semiconductorsubstrate 41. In addition, only the read/write bit lines BL1, BL2, BL3and BL4 extend in the Y-direction. For this reason, even when the numberof stacked TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 is increased, the cellarray structure is not complicated.

(5) STRUCTURAL EXAMPLES 5, 6, 7 And 8 {circle over (1)} STRUCTURALEXAMPLE 5

[0356] Structural Example 5 is a modification to Structural Examples 1,2, 3 and 4.

[0357]FIGS. 23, 24 and 25 show Structural Example 5.

[0358] The circuit diagram of FIG. 23 corresponds to that of FIG. 1 or13. The sectional view of the device structure shown in FIG. 24corresponds to that in FIGS. 4, 11, 17 and 21. The sectional view of thedevice structure shown in FIG. 25 corresponds to that in FIGS. 5, 12, 18and 22.

[0359] Structural Example 5 is different from Structural Examples 1, 2,3 and 4 in the element that implements the read select switch.

[0360] In Structural Examples 1, 2, 3 and 4, the read select switch isformed from a MOS transistor. In Structural Example 5, however, the readselect switch is formed from a diode DI.

[0361] The anode of the diode DI is connected to one terminal of each ofTMR elements MTJ1, MTJ2, MTJ3 and MTJ4 in a read block BKik. The cathodeof the diode DI is connected to a read word line RWLn (n=1, 2, . . . )

[0362] When the structure of this example is employed, in readoperation, the read word line RWLn of the selected row is set at “L”,i.e., the ground potential. With this operation, a read current can besupplied to the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 in the blocks ofthe selected row.

[0363] The device structure of Structural Example 5 can be regarded tobe substantially the same as that of Structural Example 1, 2, 3 or 4except that the element formed on the surface region of a semiconductorsubstrate 41 is the diode DI.

{circle over (2)} STRUCTURAL EXAMPLE 6

[0364] Structural Example 6 is also a modification to StructuralExamples 1, 2, 3 and 4.

[0365]FIGS. 26, 27 and 28 show Structural Example 6.

[0366] The circuit diagram of FIG. 26 corresponds to that of FIG. 1 or13. The sectional view of the device structure shown in FIG. 27corresponds to that in FIGS. 4, 11, 17 and 21. The sectional view of thedevice structure shown in FIG. 28 corresponds to that in FIGS. 5, 12, 18and 22.

[0367] As a characteristic feature of Structural Example 6, it isdifferent from Structural Examples 1, 2, 3 and 4 in the element thatimplements the read select switch. More specifically, in StructuralExample 6, the direction of a diode DI of Structural Example 5 ischanged.

[0368] That is, in Structural Example 6, the cathode of the diode DI isconnected to one terminal of each of TMR elements MTJ1, MTJ2, MTJ3 andMTJ4 in a read block BKik. The anode of the diode DI is connected to aread word line RWLn (n=1, 2, . . . )

[0369] When the structure of this example is employed, in readoperation, the read word line RWLn of the selected row is set at “H”.With this operation, a read current can be supplied to the TMR elementsMTJ1, MTJ2, MTJ3 and MTJ4 in the blocks of the selected row.

[0370] In Structural Example 5, the read current flows for a readcircuit 29B to the diode DI through the TMR elements. In StructuralExample 6, however, the read current flows from the diode DI to the readcircuit 29B through the TMR elements.

[0371] In Structural Examples 1, 2, 3 and 4, the direction of the readcurrent was not specifically described. This is because in thesestructural examples, the read current can be supplied either in thedirection in which the current is output from the read circuit 29B or inthe direction in which the current is absorbed by the read circuit 29B.

{circle over (3)} STRUCTURAL EXAMPLE 7

[0372] Structural Example 7 is a modification to Structural Examples 1and 2.

[0373]FIGS. 29 and 30 show Structural Example 7.

[0374] The circuit diagram of FIG. 29 corresponds to that of FIG. 1. Thesectional view of the device structure shown in FIG. 30 corresponds tothat in FIGS. 4 and 11.

[0375] As a characteristic feature of Structural Example 7, it isdifferent from Structural Examples 1 and 2 in the element thatimplements the read select switch.

[0376] In Structural Examples 1 and 2, the read select switch is formedfrom a MOS transistor. In Structural Example 7, however, the read selectswitch is formed from a bipolar transistor BT.

[0377] In Structural Example 7, the collector of the bipolar transistorBT is connected to one terminal of each of TMR elements MTJ1, MTJ2, MTJ3and MTJ4 in a read block BKik. The emitter of the bipolar transistor BTis connected to a source line SLi (i=1, 2, . . . , j). The base of thebipolar transistor BT is connected to a read word line RWLn (n=1, 2, . .. )

[0378] When the structure of this example is employed, in readoperation, the read word line RWLn of the selected row is set at “H”.With this operation, a read current can be supplied to the TMR elementsMTJ1, MTJ2, MTJ3 and MTJ4 in the blocks of the selected row.

[0379] The device structure of Structural Example 7 can be regarded tobe substantially the same as that of Structural Example 1 and 2 exceptthat the element formed on the surface region of a semiconductorsubstrate 41 is the bipolar transistor BT.

[0380] In the structure of this example, all transistors of a memorycell array 11 and its peripheral circuits may be bipolar transistors, orsome of them may be bipolar transistors.

{circle over (4)} STRUCTURAL EXAMPLE 8

[0381] Structural Example 8 is a modification to Structural Examples 3and 4.

[0382]FIGS. 31 and 32 show Structural Example 7.

[0383] The circuit diagram of FIG. 31 corresponds to that of FIG. 13.The sectional view of the device structure shown in FIG. 32 correspondsto that in FIGS. 17 and 21.

[0384] As a characteristic feature of Structural Example 8, it isdifferent from Structural Examples 3 and 4 in the element thatimplements the read select switch.

[0385] In Structural Examples 3 and 4, the read select switch is formedfrom a MOS transistor. In Structural Example 8, however, the read selectswitch is formed from a bipolar transistor BT.

[0386] In Structural Example 8, the collector of the bipolar transistorBT is connected to one terminal of each of TMR elements MTJ1, MTJ2, MTJ3and MTJ4 in a read block BKik. The emitter of the bipolar transistor BTis connected to a read word line RWLn (n=1, 2, . . . ) The base of thebipolar transistor BT is connected to a decode line DLi (i=1, 2, . . . ,j).

[0387] When the structure of this example is employed, in readoperation, the read word line RWLn of the selected row is set at “L”.With this operation, a read current can be supplied to the TMR elementsMTJ1, MTJ2, MTJ3 and MTJ4 in the blocks of the selected row.

[0388] The device structure of Structural Example 8 can be regarded tobe substantially the same as that of Structural Example 3 and 4 exceptthat the element formed on the surface region of a semiconductorsubstrate 41 is the bipolar transistor BT.

[0389] In the structure of this example, all transistors of a memorycell array 11 and its peripheral circuits may be bipolar transistors, orsome of them may be bipolar transistors.

[0390] (6) Others

[0391] In Structural Examples 1 to 8, read bit lines and write bit linesare put together into read/write bit lines. However, the presentinvention is not limited to this structure as long as TMR elements in aread block are connected to different read bit lines.

[0392] For example, in Structural Examples 1 to 8, read bit lines andwrite bit lines may be separately arranged. Alternatively, write wordlines may be used as read word lines.

[0393] 2. Write/Read Operation Mechanism

[0394] The write/read operation mechanism of the magnetic random accessmemory of the present invention will be briefly described.

[0395] (1) Write Operation Mechanism

[0396] A write in TMR elements is executed at random. For example, onerow is selected by row address signals. One column is selected by highorder column address signals. One of a plurality of TMR elements in readblocks in the selected row is selected by low order column addresssignals.

[0397] To write data in the selected TMR element, a write current issupplied to a write word line arranged right under the selected TMRelement. In addition, the write current is also supplied to a read/writebit line arranged on the selected TMR element. The direction of writecurrent to be supplied to the read/write bit line is determined inaccordance with the write data.

[0398] The magnetizing direction in the free layer (storing layer) ofthe selected TMR element is determined by a synthesized magnetic fieldformed by the write current flowing to the write word line and the writecurrent flowing to the read/write bit line, thereby storing “1”/“0”information in the TMR element.

[0399] (2) Read Operation Mechanism

[0400] A read from TMR elements is executed for each read block. Forexample, one row is selected by row address signals. One column isselected by high order column address signals.

[0401] To read data from a plurality of TMR elements in the selectedread block that is present on the selected row and column, a readcurrent is supplied to a plurality of read/write bit lines arranged inthe selected column. The direction of read current to be supplied to theread/write bit lines is not particularly limited.

[0402] At this time, the plurality of read/write bit lines arranged onthe selected column are preferably electrically connected only to theselected read block (for example, the circuit example shown in FIG. 3).

[0403] The potentials of the plurality of read/write bit lines havevalues corresponding to the data of the plurality of TMR elements in theread block. These potentials are sensed by a sense amplifier.

[0404] The data of the plurality of TMR elements in the selected readblock are sensed by the sense amplifier and then output from themagnetic random access memory. The bit data of the plurality of TMRelements may be output one by one or simultaneously.

[0405] To sequentially output the bit data of the plurality of TMRelements one by one, one of the plurality of TMR elements is selectedusing, e.g., low order column address signals.

[0406] 3. Examples of Peripheral Circuits

[0407] A circuit example of the write word line driver/sinker, a circuitexample of the write bit line driver/sinker, circuit examples of theread word line driver, a circuit example of the column decoder, and acircuit example of a read circuit (including a sense amplifier) will besequentially described below.

[0408] (1) Write Word Line Driver/Sinker

[0409]FIG. 33 shows a circuit example of the write word linedriver/sinker.

[0410] In this example, assume that a read block is formed from four TMRelements that are stacked at four stages, and each of the four TMRelements in the read block is selected by CA0 and CA1 of low ordercolumn address signals. FIG. 33 shows a write word line driver/sinker ofonly one row.

[0411] The write word line driver 23A-1 includes PMOS transistors QP1,QP2, QP3 and QP4, and NAND gate circuits ND1, ND2, ND3 and ND4. Thewrite word line sinker 24-1 is formed from NMOS transistors QN1, QN2,QN3 and QN4.

[0412] The PMOS transistor QP1 is connected between a power supplyterminal VDD and one end of the write word line WWL1 at the lowermoststage (first stage). The output signal from the NAND gate circuit ND1 issupplied to the gate of the PMOS transistor QP1. The NMOS transistor QN1is connected between the other end of the write word line WWL1 at thelowermost stage and the ground terminal VSS.

[0413] When the output signal from the NAND gate circuit ND1 is “0”, awrite current flows to the write word line WWL1.

[0414] The PMOS transistor QP2 is connected between the power supplyterminal VDD and one end of the write word line WWL2 at the secondstage. The output signal from the NAND gate circuit ND2 is supplied tothe gate of the PMOS transistor QP2. The NMOS transistor QN2 isconnected between the other end of the write word line WWL2 at thesecond stage and the ground terminal VSS.

[0415] When the output signal from the NAND gate circuit ND2 is “0”, awrite current flows to the write word line WWL2.

[0416] The PMOS transistor QP3 is connected between the power supplyterminal VDD and one end of the write word line WWL3 at the third stage.The output signal from the NAND gate circuit ND3 is supplied to the gateof the PMOS transistor QP3. The NMOS transistor QN3 is connected betweenthe other end of the write word line WWL3 at the third stage and theground terminal VSS.

[0417] When the output signal from the NAND gate circuit ND3 is “0”, awrite current flows to the write word line WWL3.

[0418] The PMOS transistor QP4 is connected between the power supplyterminal VDD and one end of the write word line WWL4 at the uppermoststage-(fourth stage). The output signal from the NAND gate circuit ND4is supplied to the gate of the PMOS transistor QP4. The NMOS transistorQN4 is connected between the other end of the write word line WWL4 atthe uppermost stage and the ground terminal VSS.

[0419] When the output signal from the NAND gate circuit ND4 is “0”, awrite current flows to the write word line WWL4.

[0420] Since the write word lines WWL1, WWL2, WWL3 and WWL4 belong tothe same row, the same row address signals is input to the NAND gatecircuits ND1, ND2, ND3 and ND4. In the selected row, all bits of the rowaddress signals are “H”.

[0421] A write signal is input to the NAND gate circuits ND1, ND2, ND3and ND4. In the write operation, the write signal changes to “H”. Inaddition, different low order column address signals are input to theNAND gate circuits ND1, ND2, ND3 and ND4.

[0422] That is, in this example, column address signals bCA0 and bCA1are used to select the write word line WWL1 at the lowermost stage(first stage) and input to the NAND gate circuit ND1.

[0423] The column address signals CA0 and bCA1 are used to select thewrite word line WWL2 at the second stage and input to the NAND gatecircuit ND2. The column address signals bCA0 and CA1 are used to selectthe write word line WWL3 at the third stage and input to the NAND gatecircuit ND3. The column address signals CA0 and CA1 are used to selectthe write word line WWL2 at the uppermost stage (fourth stage) and inputto the NAND gate circuit ND4.

[0424] Note that the signals bCA0 and bCA1 are inverted signals withinverted levels of CA0 and CA1.

[0425] In this write word line driver/sinker, in the write operation, awrite signal WRITE is “1”. For example, one of the output signals fromthe four NAND gate circuits ND1, ND2, ND3 and ND4 changes to “L”.

[0426] For example, when both CA0 and CA1 are “0”, all input signals tothe NAND gate circuit ND1 are “1”. The output signal from the NAND gatecircuit ND1 is “0”. As a result, the PMOS transistor QP1 is turned on.The write current flows to the write word line WWL1.

[0427] When CA0 is “1” and CA1 is “0”, all input signals to the NANDgate circuit ND2 are “1”. The output signal from the NAND gate circuitND2 is “0”. As a result, the PMOS transistor QP2 is turned on. The writecurrent flows to the write word line WWL2.

[0428] When CA0 is “0” and CA1 is “1”, all input signals to the NANDgate circuit ND3 are “1”. The output signal from the NAND gate circuitND3 is “0”. As a result, the PMOS transistor QP3 is turned on. The writecurrent flows to the write word line WWL3.

[0429] When both CA0 and CA1 are “1”, all input signals to the NAND gatecircuit ND4 are “1”. The output signal from the NAND gate circuit ND4 is“0”. As a result, the PMOS transistor QP4 is turned on. The writecurrent flows to the write word line WWL4.

[0430] (2) Write Bit Line Driver/Sinker

[0431]FIGS. 34 and 35 show a circuit example of the write bit linedriver/sinker.

[0432] In this example, assume that a read block is formed from four TMRelements that are stacked at four stages, and each of the four TMRelements in the read block is selected by CA0 and CA1 of low ordercolumn address signals. In addition, a column of the memory cell arrayis selected by high order column address signals, i.e., column addresssignals except low order two column address signals.

[0433]FIGS. 34 and 35 show a write bit line driver/sinker of only onecolumn.

[0434] The write bit line driver/sinker 29A is formed from PMOStransistors QP5, QP6, QP7 and QP8, NMOS transistors QN5, QN6, QN7 andQN8, NAND gate circuits ND5, ND6, ND7 and ND8, AND gate circuits AD1,AD2, AD3 and AD4, and inverters INV1, INV2, INV3 and INV4.

[0435] The PMOS transistor QP5 is connected between the power supplyterminal VDD and one end of the write bit line BL1 at the lowermoststage (first stage). The output signal from the NAND gate circuit ND5 issupplied to the gate of the PMOS transistor QP5. The NMOS transistor QN5is connected between one end of the write bit line BL1 at the lowermoststage and the ground terminal VSS. The output signal from the AND gatecircuit AD1 is supplied to the gate of the NMOS transistor QN5.

[0436] The PMOS transistor QP6 is connected between the power supplyterminal VDD and one end of the write bit line BL2 at the second stage.The output signal from the NAND gate circuit ND6 is supplied to the gateof the PMOS transistor QP6. The NMOS transistor QN6 is connected betweenone end of the write bit line BL2 at the second stage and the groundterminal VSS. The output signal from the AND gate circuit AD2 issupplied to the gate of the NMOS transistor QN6.

[0437] The PMOS transistor QP7 is connected between the power supplyterminal VDD and one end of the write bit line BL3 at the third stage.The output signal from the NAND gate circuit ND7 is supplied to the gateof the PMOS transistor QP7. The NMOS transistor QN7 is connected betweenone end of the write bit line BL3 at the third stage and the groundterminal VSS. The output signal from the AND gate circuit AD3 issupplied to the gate of the NMOS transistor QN7.

[0438] The PMOS transistor QP8 is connected between the power supplyterminal VDD and one end of the write bit line BL4 at the uppermoststage (fourth stage). The output signal from the NAND gate circuit ND8is supplied to the gate of the PMOS transistor QP8. The NMOS transistorQN8 is connected between one end of the write bit line BL4 at theuppermost stage and the ground terminal VSS. The output signal from theAND gate circuit AD4 is supplied to the gate of the NMOS transistor QN8.

[0439] The write bit line driver/sinker 31 is formed from PMOStransistors QP9, QP10, QP11 and QP12, NMOS transistors QN9, QN10, QN11and QN12, NAND gate circuits ND9, ND10, ND11 and ND12, AND gate circuitsAD5, AD6, AD7 and AD8, and inverters INV5, INV6, INV7 and INV8.

[0440] The PMOS transistor QP9 is connected between the power supplyterminal VDD and the other end of the write bit line BL1 at thelowermost stage (first stage). The output signal from the NAND gatecircuit ND9 is supplied to the gate of the PMOS transistor QP9. The NMOStransistor QN9 is connected between the other end of the write bit lineBL1 at the lowermost stage and the ground terminal VSS. The outputsignal from the AND gate circuit AD5 is supplied to the gate of the NMOStransistor QN9.

[0441] The PMOS transistor QP10 is connected between the power supplyterminal VDD and the other end of the write bit line BL2 at the secondstage. The output signal from the NAND gate circuit ND10 is supplied tothe gate of the PMOS transistor QP10. The NMOS transistor QN10 isconnected between the other end of the write bit line BL2 at the secondstage and the ground terminal VSS. The output signal from the AND gatecircuit AD6 is supplied to the gate of the NMOS transistor QN10.

[0442] The PMOS transistor QP11 is connected between the power supplyterminal VDD and the other end of the write bit line BL3 at the thirdstage. The output signal from the NAND gate circuit ND11 is supplied tothe gate of the PMOS transistor QP11. The NMOS transistor QN11 isconnected between the other end of the write bit line BL3 at the thirdstage and the ground terminal VSS. The output signal from the AND gatecircuit AD7 is supplied to the gate of the NMOS transistor QN11.

[0443] The PMOS transistor QP12 is connected between the power supplyterminal VDD and the other end of the write bit line BL4 at theuppermost stage (fourth stage). The output signal from the NAND gatecircuit ND12 is supplied to the gate of the PMOS transistor QP12. TheNMOS transistor QN12 is connected between the other end of the write bitline BL4 at the uppermost stage and the ground terminal VSS. The outputsignal from the AND gate circuit AD8 is supplied to the gate of the NMOStransistor QN12.

[0444] In the write bit line drivers/sinkers 29A and 31 with the abovestructures, when the output signal from the NAND gate circuit ND5 is“0”, and the output signal from the AND gate circuit AD5 is “1”, a writecurrent from the write bit line driver/sinker 29A to the write bit linedriver/sinker 31 flows to the write bit line BL1. When the output signalfrom the NAND gate circuit ND9 is “0”, and the output signal from theAND gate circuit AD1 is “1”, a write current from the write bit linedriver/sinker 31 to the write bit line driver/sinker 29A flows to thewrite bit line BL1.

[0445] When the output signal from the NAND gate circuit ND6 is “0”, andthe output signal from the AND gate circuit AD6 is “1”, a write currentfrom the write bit line driver/sinker 29A to the write bit linedriver/sinker 31 flows to the write bit line BL2.

[0446] When the output signal from the NAND gate circuit ND10 is “0”,and the output signal from the AND gate circuit AD2 is “1”, a writecurrent from the write bit line driver/sinker 31 to the write bit linedriver/sinker 29A flows to the write bit line BL2.

[0447] When the output signal from the NAND gate circuit ND7 is “0”, andthe output signal from the AND gate circuit AD7 is “1”, a write currentfrom the write bit line driver/sinker 29A to the write bit linedriver/sinker 31 flows to the write bit line BL3.

[0448] When the output signal from the NAND gate circuit ND11 is “0”,and the output signal from the AND gate circuit AD3 is “1”, a writecurrent from the write bit line driver/sinker 31 to the write bit linedriver/sinker 29A flows to the write bit line BL3.

[0449] When the output signal from the NAND gate circuit ND8 is “0”, andthe output signal from the AND gate circuit AD8 is “1”, a write currentfrom the write bit line driver/sinker 29A to the write bit linedriver/sinker 31 flows to the write bit line BL4.

[0450] When the output signal from the NAND gate circuit ND12 is “0”,and the output signal from the AND gate circuit AD4 is “1”, a writecurrent from the write bit line driver/sinker 31 to the write bit linedriver/sinker 29A flows to the write bit line BL4.

[0451] In the write bit line drivers/sinkers 29A and 31, in the writeoperation, the write signal WRITE is “1”. In the selected column, highorder column address signals, i.e., all of the column address signalsexcept the low order two column address signals CA0 and CA1 are “1”.

[0452] The low order column address signals CA0 and CA1 are used toselect one of the four write bit lines BL1, BL2, BL3 and BL4 in theselected column. A write current having a direction corresponding to thevalue of write data DATA flows to the selected bit line.

[0453] The direction of write current flowing to the selected write bitline in the selected column is determined in accordance with the valueof the write data DATA.

[0454] For example, when the write bit line BL1 is selected (whenCA0=“0” and CA1=“0”), and the write data DATA is “1”, the output signalfrom the NAND gate circuit ND5 is “0”. The output signal from the ANDgate circuit AD5 is “1”. As a result, a write current from the write bitline driver/sinker 29A to the write bit line driver/sinker 31 flows tothe write bit line BL1.

[0455] Conversely, when the write data DATA is “0”, the output signalfrom the NAND gate circuit ND9 is “0”. The output signal from the ANDgate circuit AD1 is “1”. As a result, a write current from the write bitline driver/sinker 31 to the write bit line driver/sinker 29A flows tothe write bit line BL1.

[0456] When the write bit line BL2 is selected (when CA0=“1” andCA1=“0”), and the write data DATA is “1”, the output signal from theNAND gate circuit ND6 is “0”. The output signal from the AND gatecircuit AD6 is “1”. As a result, a write current from the write bit linedriver/sinker 29A to the write bit line driver/sinker 31 flows to thewrite bit line BL2.

[0457] Conversely, when the write data DATA is “0”, the output signalfrom the NAND gate circuit ND10 is “0”. The output signal from the ANDgate circuit AD2 is “1”. As a result, a write current from the write bitline driver/sinker 31 to the write bit line driver/sinker 29A flows tothe write bit line BL2.

[0458] When the write bit line BL3 is selected (when CA0=“0” andCA1=“1”), and the write data DATA is “1”, the output signal from theNAND gate circuit ND7 is “0”. The output signal from the AND gatecircuit AD7 is “1”. As a result, a write current from the write bit linedriver/sinker 29A to the write bit line driver/sinker 31 flows to thewrite bit line BL3.

[0459] Conversely, when the write data DATA is “0”, the output signalfrom the NAND gate circuit ND11 is “0”. The output signal from the ANDgate circuit AD3 is “1”. As a result, a write current from the write bitline driver/sinker 31 to the write bit line driver/sinker 29A flows tothe write bit line BL3.

[0460] When the write bit line BL4 is selected (when CA0=“1” andCA1=“1”), and the write data DATA is “1”, the output signal from theNAND gate circuit ND8 is “0”. The output signal from the AND gatecircuit AD8 is “1”. As a result, a write current from the write bit linedriver/sinker 29A to the write bit line driver/sinker 31 flows to thewrite bit line BL4.

[0461] Conversely, when the write data DATA is “0”, the output signalfrom the NAND gate circuit ND12 is “0”. The output signal from the ANDgate circuit AD4 is “1”. As a result, a write current from the write bitline driver/sinker 31 to the write bit line driver/sinker 29A flows tothe write bit line BL4.

[0462] (3) Read Word Line Driver

[0463]FIGS. 36 and 37 show circuit examples of the read word linedriver.

[0464] The read word line driver applied to Structural Examples 1, 2, 6and 7 has a circuit structure different from that of the read word linedriver applied to Structural Examples 3, 4, 5 and 8.

[0465]FIG. 36 shows an example of the read word line driver applied toStructural Examples 1, 2, 6 and 7.

[0466] The read word line driver 23B-1 is formed from an AND gatecircuit AD9. A read signal READ and row address signals are input to theAND gate circuit AD9.

[0467] In the read operation, the read signal is “1”. The row addresssignals are the same as that in the write word line driver/sinker (FIG.33).

[0468] In the read operation, in the selected row, all of the rowaddress signals are “1”. Hence, the potential of the read word line RWL1is “1”.

[0469]FIG. 37 shows an example of the read word line driver applied toStructural Examples 3, 4, 5 and 8.

[0470] The read word line driver 23B-1 is formed from a NAND gatecircuit ND13. The read signal READ and row address signal are input tothe NAND gate circuit ND13.

[0471] In the read operation, the read signal is “1”. The row addresssignals are the same as that in the write word line driver/sinker (FIG.33). n the read operation, in the selected row, all of the row addresssignals are “1”. Hence, the potential of the read word line RWL1 is “0”.

[0472] (4) Column Decoder

[0473]FIGS. 38 and 39 show a circuit example of the column decoder.

[0474] Each of the column decoders 32, 32A and 32B is formed from an ANDgate circuit AD10. The read signal READ and high order column addresssignals are input to the AND gate circuit AD10. In the read operation,the read signal is “1”. In the selected column, all of the high ordercolumn address signals are “1”.

[0475] Hence, in the column decoder 32 or 32A, the potential of thecolumn select signal CSLj as its output signal is set to “1”. In thecolumn decoder 32B, the decode signal DL1 as its output signal is set to“1”.

[0476] (5) Read Circuit

[0477]FIG. 40 shows an example of the block diagram of the read circuit.

[0478] In this example, assume that, four TMR elements are arranged inone read block of one column, and the TMR elements are independentlyconnected to read bit lines. That is, four read bit lines are arrangedon one column. These read bit lines are connected to the read circuit29B through the column select switch.

[0479] The read circuit 29B of this example is applied to a 1-I/O-typemagnetic random access memory which outputs read data bits one by one.

[0480] Hence, the read circuit 29B has four sense amplifiers & biascircuits 29B11, 29B12, 29B13 and 29B14, a selector 29B2, and an outputbuffer 29B3.

[0481] In the read operation, read data are simultaneously read fromfour TMR elements in the selected read block. These four read data areinput to and sensed by the sense amplifiers & bias circuits 29B11,29B12, 29B13 and 29B14, respectively.

[0482] On the basis of the low order column address signal CA0 and CA1,the selector 29B2 selects one of the four read data output from thesense amplifiers & bias circuits 29B11, 29B12, 29B13 and 29B14. Theselected read data is output from the magnetic random access memory asoutput data through the output buffer 29B3.

[0483] In this example, the read circuit 29B is applied to a 1-I/O-typemagnetic random access memory.

[0484] However, when the read circuit 29B is applied to, e.g., a4-I/O-type magnetic random access memory which outputs 4-bit read data,the selector 29B2 can be omitted. To the contrary, four output buffers29B3 are required in correspondence with the sense amplifiers & biascircuits 29B11, 29B12, 29B13 and 29B14.

[0485]FIG. 41 shows an example of the block diagram of the read circuitapplied to a 4-I/O-type magnetic random access memory.

[0486] The read circuit 29B has four sense amplifiers & bias circuits29B11, 29B12, 29B13 and 29B14 and four output buffers 29B31, 29B32,29B33 and 29B34.

[0487] In the read operation, read data are simultaneously read fromfour TMR elements in the selected read block. These four read data areinput to and sensed by the sense amplifiers & bias circuits 29B11,29B12, 29B13 and 29B14, respectively.

[0488] The output data from the sense amplifiers & bias circuits 29B11,29B12, 29B13 and 29B14 are output from the magnetic random access memorythrough the output buffers 29B31, 29B32, 29B33 and 29B34.

[0489]FIG. 42 shows a circuit example of the sense amplifier & biascircuit.

[0490] This sense amplifier & bias circuit corresponds to one of thefour sense amplifiers & bias circuits shown in FIG. 40 or 41.

[0491] A sense amplifier S/A is formed from, e.g., a differentialamplifier.

[0492] A PMOS transistor QP14 and NMOS transistor QN13 are connected inseries between the power supply terminal VDD and the column selectswitch 29C. The negative input terminal of a differential amplifier OPis connected to a node n2. The output terminal of the differentialamplifier OP is connected to the gate of the NMOS transistor QN13. Aclamp potential VC is input to the positive input terminal of thedifferential amplifier OP.

[0493] The differential amplifier OP equalizes the potential of the noden2 with the clamp potential VC. The clamp potential VC is set to apredetermined positive value.

[0494] A constant current source Is1 generates a read current Iread. Theread current Iread flows to a bit line BLi through a current mirrorcircuit formed from a PMOS transistor QP13 and the PMOS transistor QP14.The sense amplifier formed from, e.g., a differential amplifier sensesthe data of a memory cell (TMR element) on the basis of the potential ofa node n1 when the read current Iread is flowing.

[0495]FIG. 43 shows a circuit example of the sense amplifier. FIG. 44shows a circuit example of the reference potential generating circuit ofthe sense amplifier.

[0496] The sense amplifier S/A is formed from, e.g., a differentialamplifier shown in FIG. 45. The sense amplifier S/A compares a potentialVn1 of the node n1 with a reference potential Vref.

[0497] The reference potential Vref is generated by a TMR element whichstores “1” data and a TMR element which stores “0” data.

[0498] A PMOS transistor QP16 and NMOS transistors QN14 and QN15 areconnected in series between the power supply terminal VDD and the TMRelement which stores “1” data. A PMOS transistor QP17 and NMOStransistors QN16 and QN17 are connected in series between the powersupply terminal VDD and the TMR element which stores “0” data.

[0499] The drains of the PMOS transistors QP16 and QP17 are connected toeach other. The drains of the NMOS transistors QN15 and QN17 are alsoconnected to each other.

[0500] The differential amplifier OP equalizes the potential of a noden4 with the clamp potential VC. A constant current source Is2 generatesthe read current Iread. The read current Iread flows to the TMR elementwhich stores “1” data and TMR element which stores “0” data through acurrent mirror circuit formed from the PMOS transistors QP15 and QP16.

[0501] The reference potential Vref is output from a node n3.

[0502] Assume that Is1=Is2, the transistors QP13, QP14, QP15, QP16 andQP17 have the same size, the transistors QN13, QN14 and QN16 have thesame size, and the transistors QN15 and QN17 and NMOS transistors towhich CSL1, CSL2, . . . are input have the same size. In this case, thereference potential Vref can be set to the intermediate value betweenthe potential Vn1 when “1” data is output and that when “0” data isoutput.

[0503]FIG. 45 shows a circuit example of the differential amplifier OPshown in FIGS. 42 and 44.

[0504] The differential amplifier OP is formed from PMOS transistorsQP18 and QP19 and NMOS transistors QN18, QN19 and QN20. When an enablesignal Enable changes to “H”, the differential amplifier OP is set in anoperative state.

[0505] 4. Manufacturing Method

[0506] The cell array structure, read operation mechanism, and readcircuit of the magnetic random access memory of the present inventionhave been described above. Finally, a manufacturing method forimplementing the magnetic random access memory of the present inventionwill be described.

[0507] The manufacturing method to be described below is related toStructural Example 1. Structural Examples 2 to 8 can also easily beformed using the following manufacturing method.

[0508] Structural Example 2 is different from Structural Example 1 onlyin the direction of read select switch. Structural Examples 3 and 4 aredifferent from Structural Example 1 only in the type (purpose) ofinterconnection connected to the read select switch. Structural Examples5 to 8 are different from Structural Example 1 only in the element thatconstructs the read select switch.

[0509] (1) Cell Array Structure to be Manufactured

[0510] The cell array structure completed by the manufacturing method ofthe present invention will be briefly described first. Then, themanufacturing method of the cell array structure will be described.

[0511]FIG. 46 shows the cell array structure related to StructuralExample 1.

[0512] In this cell array structure, one read block is formed by fourTMR elements MTJ1, MTJ2, MTJ3 and MTJ4 that are vertically stacked.

[0513] Read select switches (MOS transistors) RSW are arranged on thesurface region of a semiconductor substrate 51. The read select switchesRSW in two read blocks adjacent in the Y-direction share one source. Thesource of the read select switch RSW is connected to a source line SL.The source line SL extends straight in, e.g., the Y-direction and iscommonly connected to the read select switches RSW in a plurality ofread blocks arranged in one column.

[0514] The gates of the read select switches (MOS transistors) RSW serveas read word lines RWL1, RWL2 and RWL3. The read word lines RWL1, RWL2and RWL3 extend in the X-direction. The four TMR elements MTJ1, MTJ2,MTJ3 and MTJ4 are stacked on each read select switch RSW.

[0515] Each of the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 has, e.g., thestructure shown in FIG. 7, 8 or 9. As for the vertical direction of theTMR elements MTJ1, MTJ2, MTJ3 and MTJ4, for example, the free layer(storing layer) is separated equidistantly from the write word line andread/write bit line as much as possible. Its axis of easy magnetizationis set to be parallel to, e.g., the X-direction.

[0516] The lower surfaces of the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4are connected to lower electrodes. The lower electrodes are connected tothe drain of the read select switch (MOS transistor) RSW through contactplugs.

[0517] Write word lines WWL1, WWL2, WWL3 and WWL4 extending in theX-direction are arranged right under the TMR elements MTJ1, MTJ2, MTJ3and MTJ4, respectively. The upper surfaces of the TMR elements MTJ1,MTJ2, MTJ3 and MTJ4 are in contact with read/write bit lines BL1, BL2,BL3 and BL4 extending in the Y-direction.

[0518] When the cell array structure is viewed from the upper side ofthe semiconductor substrate 51, for example, the TMR elements MTJ1,MTJ2, MTJ3 and MTJ4 are laid out to overlap each other. The write wordlines WWL1, WWL2, WWL3 and WWL4 are also laid out to overlap each other.The read/write bit lines BL1, BL2, BL3 and BL4 are also laid out tooverlap each other.

[0519] The contact plugs for connecting the terminals of the TMRelements MTJ1, MTJ2, MTJ3 and MTJ4 to the drain of the read selectswitch RSW are laid out not to overlap the write word lines WWL1, WWL2,WWL3 and WWL4 and read/write bit lines BL1, BL2, BL3 and BL4.

[0520] (2) Steps in Manufacturing Method

[0521] The manufacturing method for implementing the cell arraystructure shown in FIG. 46 will be described below. A detailedmanufacturing method (e.g., employment of a dual damascene process) willbe described here. Hence, note that elements that are not illustrated inthe cell array structure of FIG. 46 will be mentioned. However, theoutline of the finally completed cell array structure is almost the sameas that shown in FIG. 46.

[0522] [1] Active Region Isolation Step

[0523] First, as shown in FIG. 47, active areas are isolated by theshallow trench isolation (STI) method in the semiconductor substrate 51.

[0524] Field oxide films 52 are filled in shallow trenches, e.g., thefollowing process.

[0525] A mask pattern (e.g., a silicon nitride film) is formed on thesemiconductor substrate 51 by PEP (Photo Engraving Process). Thesemiconductor substrate 51 is etched by RIE (Reactive Ion Etching) usingthe mask pattern as a mask to form trenches in the semiconductorsubstrate 51. These trenches are filled with an insulating material(e.g., a silicon oxide) using, e.g., CVD (Chemical Vapor Deposition) andCMP (Chemical Mechanical Polishing).

[0526] After that, p-type impurities (e.g., B or BF₂) or n-typeimpurities (e.g., P or As) are doped into the semiconductor substrateby, e.g., the ion implantation technique, as needed, to form p-type wellregions or n-type well regions.

[0527] [2] MOSFET Forming Step

[0528] Next, as shown in FIG. 48, MOS transistors including the readselect switches are formed on the surface region of the semiconductorsubstrate 51.

[0529] The MOS transistors can be formed by, e.g., the followingprocess.

[0530] Impurities for controlling the threshold value of the MOStransistors are ion-implanted into necessitate channel portions inactive areas surrounding by field oxides 52. A gate insulating film(e.g., a silicon oxide film) 53 is formed in the active areas by thermaloxidation. A gate electrode material (e.g., polysilicon containingimpurities) and cap insulating film (e.g., a silicon nitride film) 55are formed on the gate insulating film 53 by CVD.

[0531] The cap insulating film 55 is patterned by PEP. Then, the gateelectrode material and gate insulating film 53 are processed (etched) byRIE using the cap insulating film 55 as a mask. As a consequence, gateelectrodes 54 extending in the X-direction are formed on thesemiconductor substrate 51.

[0532] P- or n-type impurities is doped into the semiconductor substrate51 by ion implantation using the cap insulating film 55 and gateelectrodes 54 as a mask. Lightly-doped impurity regions (LDD regions orextension regions) are formed in the semiconductor substrate.

[0533] An insulating film (e.g., a silicon nitride film) is formed onthe entire surface of the semiconductor substrate 51 by CVD. After that,the insulating film is etched by RIE to form sidewall insulating layers57 on the side surfaces of the gate electrodes 54 and cap insulatingfilms 55. P- or n-type impurities is doped into the semiconductorsubstrate 51 by ion implantation using the cap insulating films 55, gateelectrodes 54, and sidewall insulating layers 57 as a mask. As a result,source regions 56A and drain regions 56B are formed in the semiconductorsubstrate 51.

[0534] After that, a dielectric interlayer (e.g., a silicon oxide layer)58 that completely covers the MOS transistors is formed on the entiresurface of the semiconductor substrate 51 by CVD. In addition, thesurface of the dielectric interlayer 58 is planarized by CMP.

[0535] [3] Contact Hole Forming Step

[0536] Next, as shown in FIGS. 49 and 50, contact holes 59 that reachthe source regions 56A and drain regions 56B of MOS transistors areformed in the dielectric interlayer 58 on the semiconductor substrate51.

[0537] The contact holes 59 can easily be formed by, e.g., forming aphotoresist pattern on the dielectric interlayer 58 by PEP and etchingthe dielectric interlayer 58 by RIE using the photoresist pattern as amark. After etching, the photoresist pattern is removed.

[0538] [4] Interconnection Trench Forming Step

[0539] As shown in FIG. 51, interconnection trenches 60 are formed inthe dielectric interlayer 58 on the semiconductor substrate 51. In thisexample, the interconnection trenches 60 extend in the Y-direction. Thecontact holes 59 on the source regions 56A, the contact holes 59 on thedrain regions 56B, and the interconnection trenches 60 do notsimultaneously appear in the same section (a section obtained by cuttingthe device along a straight line that extends in the Y-direction).

[0540] The interconnection trenches 60 are indicated by broken lines inFIG. 51.

[0541] The interconnection trenches 60 can easily be formed by, e.g.,forming a photoresist pattern on the dielectric interlayer 58 by PEP andetching the dielectric interlayer 58 by RIE using the photoresistpattern as a mark. After etching, the photoresist pattern is removed.

[0542] [5] First Interconnection Layer Forming Step

[0543] As shown in FIG. 52, a barrier metal layer (e.g., a multi-layerof Ti and TiN) 61 is formed on the dielectric interlayer 58, the innersurfaces of the contact holes 59, and the inner surfaces of theinterconnection trenches 60 by, e.g., sputtering. Subsequently, a metallayer (e.g., a W layer) 62 that completely fills the contact holes 59and interconnection trenches 60 is formed on the barrier metal layer 61by, e.g., sputtering.

[0544] After that, as shown in FIG. 53, the metal layer 62 is polishedby, e.g., CMP and left only in the contact holes 59 and interconnectiontrenches 60. The metal layer 62 remaining in each contact hole 59 formsa contact plug 62A. The metal layer 62 remaining in each interconnectiontrench 60 forms a first interconnection layer (source line or decodeline) 62B. A dielectric interlayer (e.g., a silicon oxide layer) 63 isformed on the dielectric interlayer 58 by CVD.

[0545] The step comprising the contact hole forming step, theinterconnection trench forming step, and the first interconnection layerforming step is called the dual damascene process.

[0546] Actually, the contact plugs 62A and first interconnection layers62B do not simultaneously appear in the same section (a section obtainedby cutting the device along a straight line that extends in theY-direction). However, FIG. 53 and subsequent drawings from FIG. 54 (tobe described below) show not only the contact plugs 62A but also thefirst interconnection layers 62B that do not actually appear as asection.

[0547] [6] Interconnection Trench Forming Step

[0548] Next, as shown in FIG. 54, interconnection trenches 64 are formedin the dielectric interlayer 63. In this example, the interconnectiontrenches 64 serve as trenches used to form write word lines and extendin the X-direction. If the metal layer material is Cu, sidewallinsulating layers (such as silicon nitride) are needed for preventingfrom Cu diffusion and corrosion are formed on the side surfaces of theinterconnection trenches 64.

[0549] The interconnection trenches 64 can easily be formed by, e.g.,forming a photoresist pattern on the dielectric interlayer 63 by PEP andetching the dielectric interlayer 63 by RIE using the photoresistpattern as a mask. After etching, the photoresist pattern is removed.

[0550] The sidewall insulating layers 65 can easily be formed by formingan insulating film (e.g., a silicon nitride film) on the entire surfaceof the dielectric interlayer 63 by CVD and etching the insulating filmby RIE.

[0551] [7] Second Interconnection Layer Forming Step

[0552] As shown in FIG. 55, a barrier metal layer (e.g., a multi-layerof Ta and TaN) 66 is formed on the dielectric interlayer 63, the innersurfaces of the interconnection trenches 64, and the sidewall insulatinglayers 65 by, e.g., sputtering. Subsequently, a metal layer (e.g., a Culayer) 67 that completely fills the interconnection trenches 64 isformed on the barrier metal layer 66 by, e.g., sputtering orelectroplating.

[0553] After that, as shown in FIG. 56, the metal layer 67 is polishedby, e.g., CMP and left only in the interconnection trenches 64. Themetal layer 67 remaining in each interconnection trench 64 forms asecond interconnection layer that functions as a write word line.

[0554] An insulating layer (e.g., a silicon nitride layer) 68 is formedon the dielectric interlayer 63 by CVD. If needed, the insulating layer68 is polished by CMP and left only on the metal layers 67 serving asthe second interconnection layers. In addition, a dielectric interlayer(e.g., a silicon oxide layer) 69 that completely covers the metal layers67 serving as the second interconnection layers is formed on thedielectric interlayer 63.

[0555] The step comprising the interconnection trench forming step andthe second interconnection layer forming step is called the damasceneprocess.

[0556] [8] Step of Forming Lower Electrode of First MTJ Element

[0557] Next, as shown in FIGS. 57 and 58, contact holes that reach themetal layers 62A and 62B serving as the first interconnection layers areformed in the dielectric interlayer 69.

[0558] These contact holes can easily be formed by, e.g., forming aphotoresist pattern on the dielectric interlayer 69 by PEP and etchingthe dielectric interlayers 63 and 69 by RIE using the photoresistpattern as a mask. After etching, the photoresist pattern is removed.

[0559] In addition, a barrier metal layer (e.g., a multi-layer of Ti andTiN) 70 is formed on the inner surfaces of the contact holes by, e.g.,sputtering. Subsequently, a metal layer (e.g., a W layer) 71 thatcompletely fills the contact holes is formed on the barrier metal layer70 by, e.g., sputtering.

[0560] After that, the metal layer 71 is polished by, e.g., CMP and leftonly in the contact holes. The metal layer 71 remaining in each contacthole forms a contact plug. In addition, metal layers (e.g., Ta layers)72 serving as the lower electrodes of the first MTJ elements are formedon the dielectric interlayer 69 by CVD.

[0561] [9] First MTJ Element Forming Step

[0562] As shown in FIGS. 59 and 60, first MTJ elements 73 are formed onthe metal layers 72. Each first MTJ element 73 has, as its main portion,a tunneling barrier and two ferromagnetic layers that sandwich thetunneling barrier, and has, e.g., the structure as shown in FIG. 7.

[0563] The lower electrodes 72 of the first MTJ elements 73 arepatterned.

[0564] The lower electrodes 72 of the first MTJ elements 73 can easilybe patterned by forming a photoresist pattern on the lower electrodes 72by PEP and etching the lower electrodes 72 by RIE using the photoresistpattern as a mask. Then, the photoresist pattern is removed.

[0565] After that, a dielectric interlayer 75 that completely covers thefirst MTJ elements 73 is formed by CVD.

[0566] [10] Interconnection Trench Forming Step

[0567] As shown in FIG. 61, interconnection trenches 75A are formed inthe dielectric interlayer 75. In this example, the interconnectiontrenches 75A serve as trenches used to form read/write bit lines andextend in the Y-direction. If the metal layer material is Cu, sidewallinsulating layers (such as silicon nitride) are needed for preventingfrom Cu diffusion and corrosion are formed on the side surfaces of theinterconnection trenches 75A.

[0568] The interconnection trenches 75A can easily be formed by, e.g.,forming a photoresist pattern on the dielectric interlayer 75 by PEP andetching the dielectric interlayer 75 by RIE using the photoresistpattern as a mask. After etching, the photoresist pattern is removed.

[0569] The sidewall insulating layers can easily be formed by forming aninsulating film (e.g., a silicon nitride film) on the entire surface ofthe dielectric interlayer 75 by CVD and etching the insulating film byRIE.

[0570] [11] Third Interconnection Layer Forming Step

[0571] As shown in FIG. 62, a barrier metal layer (e.g., a multi-layerof Ta and TaN) 76 is formed on the dielectric interlayer 75, the innersurfaces of the interconnection trenches 75A, and the sidewallinsulating layers by, e.g., sputtering. Subsequently, a metal layer(e.g., a Cu layer) 77 that completely fills the interconnection trenches75A is formed on the barrier metal layer 76 by, e.g., sputtering orelectroplating.

[0572] After that, as shown in FIG. 63, the metal layer 77 is polishedby, e.g., CMP and left only in the interconnection trenches 75A. Themetal layer 77 remaining in each interconnection trench 75A forms athird interconnection layer that functions as a read/write bit line.

[0573] An insulating layer (e.g., a silicon nitride layer) 78 is formedon the dielectric interlayer 75 by CVD. If needed, the insulating layer78 is polished by CMP and left only on the metal layers 77 serving asthe third interconnection layers. In addition, a dielectric interlayer(e.g., a silicon oxide layer) 79 that completely covers the metal layers77 serving as the third interconnection layers is formed on thedielectric interlayer 75.

[0574] [12] Interconnection Trench Forming Step

[0575] Next, as shown in FIG. 64, interconnection trenches 87 are formedin the dielectric interlayer 79. In this example, the interconnectiontrenches 87 serve as trenches used to form write word lines and extendin the X-direction. If the metal layer material is Cu, sidewallinsulating layers (such as silicon nitride) are needed for preventingfrom Cu diffusion and corrosion are formed on the side surfaces of theinterconnection trenches 87.

[0576] The interconnection trenches 87 can easily be formed by, e.g.,forming a photoresist pattern on a dielectric interlayer 86 by PEP andetching the dielectric interlayer 86 by RIE using the photoresistpattern as a mask. After etching, the photoresist pattern is removed.

[0577] The sidewall insulating layers 88 can easily be formed by formingan insulating film (e.g., a silicon nitride film) on the entire surfaceof the dielectric interlayer 86 by CVD and etching the insulating filmby RIE.

[0578] [13] Fourth Interconnection Layer Forming Step

[0579] As shown in FIG. 65, a barrier metal layer (e.g., a multi-layerof Ta and TaN) 89 is formed on the dielectric interlayer 79, the innersurfaces of the interconnection trenches 87, and the sidewall insulatinglayers 88 by, e.g., sputtering. Subsequently, a metal layer (e.g., a Culayer) 91 that completely fills the interconnection trenches 87 isformed on the barrier metal layer 89 by, e.g., sputtering orelectroplating.

[0580] After that, as shown in FIG. 66, the metal layer 91 is polishedby, e.g., CMP and left only in the interconnection trenches 87. Themetal layer 91 remaining in each interconnection trench 87 forms afourth interconnection layer that functions as a write word line.

[0581] An insulating layer (e.g., a silicon nitride layer) 92 is formedon the dielectric interlayer 86 by CVD. If needed, the insulating layer92 is polished by CMP and left only on the metal layers 91 serving asthe fourth interconnection layers. In addition, a dielectric interlayer(e.g., a silicon oxide layer) 93 that completely covers the metal layers91 serving as the fourth interconnection layers is formed on thedielectric interlayer 86.

[0582] [14] Step of Forming Lower Electrode of Second MTJ Element

[0583] Next, as shown in FIGS. 67 and 68, contact holes that reach thelower electrodes 72 of the first MTJ elements are formed in thedielectric interlayers 79 and 93.

[0584] These contact holes can easily be formed by, e.g., forming aphotoresist pattern on the dielectric interlayer 93 by PEP and etchingthe dielectric interlayers 79 and 93 by RIE using the photoresistpattern as a mask. After etching, the photoresist pattern is removed.

[0585] In addition, a barrier metal layer (e.g., a multi-layer of Ti andTiN) 94 is formed on the inner surfaces of the contact holes by, e.g.,sputtering. Subsequently, a metal layer (e.g., a W layer) 95 thatcompletely fills the contact holes is formed on the barrier metal layer94 by, e.g., sputtering.

[0586] After that, the metal layer 95 is polished by, e.g., CMP and leftonly in the contact holes. The metal layer 95 remaining in each contacthole forms a contact plug. In addition, metal layers (e.g., Ta layers)96 serving as the lower electrodes of the second MTJ elements are formedon the dielectric interlayer 93 by sputtering.

[0587] [15] Second MTJ Element Forming Step

[0588] As shown in FIGS. 69 and 70, second MTJ elements 97 are formed onthe metal layers 96. Each second MTJ element 97 has, as its mainportion, a tunneling barrier and two ferromagnetic layers that sandwichthe tunneling barrier, and has, e.g., the structure as shown in FIG. 7.

[0589] The lower electrodes 96 of the second MTJ elements 97 arepatterned.

[0590] The lower electrodes 96 of the second MTJ elements 97 can easilybe patterned by forming a photoresist pattern on the lower electrodes 96by PEP and etching the lower electrodes 96 by RIE using the photoresistpattern as a mask. Then, the photoresist pattern is removed.

[0591] After that, a dielectric interlayer 100 that completely coversthe second MTJ elements 97 is formed by CVD.

[0592] [16] Interconnection Trench Forming Step

[0593] As shown in FIG. 71, interconnection trenches 100A are formed inthe dielectric interlayer 100. In this example, the interconnectiontrenches 100A serve as trenches used to form read/write bit lines andextend in the Y-direction. If the metal layer material is Cu, sidewallinsulating layers (such as silicon nitride) are needed for preventingfrom Cu diffusion and corrosion are formed on the side surfaces of theinterconnection trenches 100A.

[0594] The interconnection trenches 100A can easily be formed by, e.g.,forming a photoresist pattern on the dielectric interlayer 100 by PEPand etching the dielectric interlayer 100 by RIE using the photoresistpattern as a mask. After etching, the photoresist pattern is removed.

[0595] The sidewall insulating layers can easily be formed by forming aninsulating film (e.g., a silicon nitride film) on the entire surface ofthe dielectric interlayer 100 by CVD and etching the insulating film byRIE.

[0596] [17] Fifth Interconnection Layer Forming Step

[0597] As shown in FIG. 72, a barrier metal layer (e.g., a multi-layerof Ta and TaN) 101 is formed on the dielectric interlayer 100, the innersurfaces of the interconnection trenches 100A, and the sidewallinsulating layers by, e.g., sputtering. Subsequently, a metal layer(e.g., a Cu layer) 102 that completely fills the interconnectiontrenches 100A is formed on the barrier metal layer 101 by, e.g.,sputtering or electroplating.

[0598] After that, as shown in FIG. 73, the metal layer 102 is polishedby, e.g., CMP and left only in the interconnection trenches 100A. Themetal layer 102 remaining in each interconnection trench 100A forms afifth interconnection layer that functions as a read/write bit line.

[0599] An insulating layer (e.g., a silicon nitride layer) 103 is formedon the dielectric interlayer 100 by CVD. If needed, the insulating layer103 is polished by CMP and left only on the metal layers 102 serving asthe fifth interconnection layers. In addition, a dielectric interlayer(e.g., a silicon oxide layer) 104 that completely covers the metallayers 102 serving as the fifth interconnection layers is formed on thedielectric interlayer 100.

[0600] [18] Interconnection Trench Forming Step

[0601] Next, as shown in FIG. 74, interconnection trenches 112 areformed in the dielectric interlayer 104. In this example, theinterconnection trenches 112 serve as trenches used to form write wordlines and extend in the X-direction. If the metal layer material is Cu,sidewall insulating layers (such as silicon nitride) are needed forpreventing from Cu diffusion and corrosion are formed on the sidesurfaces of the interconnection trenches 112.

[0602] The interconnection trenches 112 can easily be formed by, e.g.,forming a photoresist pattern on the dielectric interlayer 104 by PEPand etching the dielectric interlayer 104 by RIE using the photoresistpattern as a mask. After etching, the photoresist pattern is removed.

[0603] The sidewall insulating layers 113 can easily be formed byforming an insulating film (e.g., a silicon nitride film) on the entiresurface of the dielectric interlayer 104 by CVD and etching theinsulating film by RIE.

[0604] [19] Sixth Interconnection Layer Forming Step

[0605] As shown in FIG. 75, a barrier metal layer (e.g., a multi-layerof Ta and TaN) 114 is formed on the dielectric interlayer 104, the innersurfaces of the interconnection trenches 112, and the sidewallinsulating layers 113 by, e.g., sputtering. Subsequently, a metal layer(e.g., a Cu layer) 115 that completely fills the interconnectiontrenches 112 is formed on the barrier metal layer 114 by, e.g.,sputtering or electroplating.

[0606] After that, as shown in FIG. 76, the metal layer 115 is polishedby, e.g., CMP and left only in the interconnection trenches 112. Themetal layer 115 remaining in each interconnection trench 112 forms asixth interconnection layer that functions as a write word line.

[0607] An insulating layer (e.g., a silicon nitride layer) 116 is formedon the dielectric interlayer 104 by CVD. If needed, the insulating layer116 is polished by CMP and left only on the metal layers 115 serving asthe sixth interconnection layers. In addition, a dielectric interlayer(e.g., a silicon oxide layer) 117 that completely covers the metallayers 115 serving as the sixth interconnection layers is formed on thedielectric interlayer 104.

[0608] [20] Step of Forming Lower Electrode of Third MTJ Element

[0609] Next, as shown in FIGS. 77 and 78, contact holes that reach thelower electrodes 96 of the second MTJ elements are formed in thedielectric interlayers 100 and 104.

[0610] These contact holes can easily be formed by, e.g., forming aphotoresist pattern on the dielectric interlayer 104 by PEP and etchingthe dielectric interlayers 100 and 104 by RIE using the photoresistpattern as a mask. After etching, the photoresist pattern is removed.

[0611] In addition, a barrier metal layer (e.g., a multi-layer of Ti andTiN) 118 is formed on the inner surfaces of the contact holes by, e.g.,sputtering. Subsequently, a metal layer (e.g., a W layer) 119 thatcompletely fills the contact holes is formed on the barrier metal layer118 by, e.g., sputtering.

[0612] After that, the metal layer 119 is polished by, e.g., CMP andleft only in the contact holes. The metal layer 119 remaining in eachcontact hole forms a contact plug. In addition, metal layers (e.g., Talayers) 120 serving as the lower electrodes of the third MTJ elementsare formed on the dielectric interlayer 117 by sputtering.

[0613] [21] Third MTJ Element Forming Step

[0614] As shown in FIGS. 79 and 80, third MTJ elements 121 are formed onthe metal layers 120. Each third MTJ element 121 has, as its mainportion, a tunneling barrier and two ferromagnetic layers that sandwichthe tunneling barrier, and has, e.g., the structure as shown in FIG. 7.

[0615] The lower electrodes 120 of the third MTJ elements 121 arepatterned.

[0616] The lower electrodes 120 of the third MTJ elements 121 can easilybe patterned by forming a photoresist pattern on the lower electrodes120 by PEP and etching the lower electrodes 120 by RIE using thephotoresist pattern as a mask. Then, the photoresist pattern is removed.

[0617] After that, a dielectric interlayer 122 that completely coversthe third MTJ elements 121 is formed by CVD.

[0618] [22] Interconnection Trench Forming Step

[0619] As shown in FIG. 81, interconnection trenches 122A are formed inthe dielectric interlayer 122. In this example, the interconnectiontrenches 122A serve as trenches used to form read/write bit lines andextend in the Y-direction. If the metal layer material is Cu, sidewallinsulating layers (such as silicon nitride) are needed for preventingfrom Cu diffusion and corrosion are formed on the side surfaces of theinterconnection trenches 122A.

[0620] The interconnection trenches 122A can easily be formed by, e.g.,forming a photoresist pattern on the dielectric interlayer 122 by PEPand etching the dielectric interlayer 122 by RIE using the photoresistpattern as a mask. After etching, the photoresist pattern is removed.

[0621] The sidewall insulating layers can easily be formed by forming aninsulating film (e.g., a silicon nitride film) on the entire surface ofthe dielectric interlayer 122 by CVD and etching the insulating film byRIE.

[0622] [23] Seventh Interconnection Layer Forming Step

[0623] As shown in FIG. 82, a barrier metal layer (e.g., a multi-layerof Ta and TaN) 123 is formed on the dielectric interlayer 122, the innersurfaces of the interconnection trenches 122A, and the sidewallinsulating layers by, e.g., sputtering. Subsequently, a metal layer(e.g., a Cu layer) 124 that completely fills the interconnectiontrenches 122A is formed on the barrier metal layer 123 by, e.g.,sputtering or electroplating.

[0624] After that, as shown in FIG. 83, the metal layer 124 is polishedby, e.g., CMP and left only in the interconnection trenches 122A. Themetal layer 124 remaining in each interconnection trench 122A forms aseventh interconnection layer that functions as a read/write bit line.

[0625] An insulating layer (e.g., a silicon nitride layer) 125 is formedon the dielectric interlayer 122 by CVD. If needed, the insulating layer125 is polished by CMP and left only on the metal layers 124 serving asthe seventh interconnection layers. In addition, a dielectric interlayer(e.g., a silicon oxide layer) 126 that completely covers the metallayers 124 serving as the seventh interconnection layers is formed onthe dielectric interlayer 122.

[0626] [24] Interconnection Trench Forming Step

[0627] Next, as shown in FIG. 84, interconnection trenches 127 areformed in the dielectric interlayer 126. In this example, theinterconnection trenches 127 serve as trenches used to form write wordlines and extend in the X-direction. If the metal layer material is Cu,sidewall insulating layers (such as silicon nitride) are needed forpreventing from Cu diffusion and corrosion are formed on the sidesurfaces of the interconnection trenches 127.

[0628] The interconnection trenches 127 can easily be formed by, e.g.,forming a photoresist pattern on the dielectric interlayer 126 by PEPand etching the dielectric interlayer 126 by RIE using the photoresistpattern as a mask. After etching, the photoresist pattern is removed.

[0629] The sidewall insulating layers 128 can easily be formed byforming an insulating film (e.g., a silicon nitride film) on the entiresurface of the dielectric interlayer 126 by CVD and etching theinsulating film by RIE.

[0630] [25] Eighth Interconnection Layer Forming Step

[0631] As shown in FIG. 85, a barrier metal layer (e.g., a multi-layerof Ta and TaN) 129 is formed on the dielectric interlayer 126, the innersurfaces of the interconnection trenches 127, and the sidewallinsulating layers 128 by, e.g., sputtering. Subsequently, a metal layer(e.g., a Cu layer) 130 that completely fills the interconnectiontrenches 127 is formed on the barrier metal layer 129 by, e.g.,sputtering or electroplating.

[0632] After that, as shown in FIG. 86, the metal layer 130 is polishedby, e.g., CMP and left only in the interconnection trenches 127. Themetal layer 130 remaining in each interconnection trench 127 forms aneighth interconnection layer that functions as a write word line.

[0633] An insulating layer (e.g., a silicon nitride layer) 131 is formedon the dielectric interlayer 126 by CVD. If needed, the insulating layer131 is polished by CMP and left only on the metal layers 130 serving asthe eighth interconnection layers. In addition, a dielectric interlayer(e.g., a silicon oxide layer) 132 that completely covers the metallayers 130 serving as the eighth interconnection layers is formed on thedielectric interlayer 126.

[0634] [26] Step of Forming Lower Electrode of Fourth MTJ Element

[0635] Next, as shown in FIGS. 87 and 88, contact holes that reach thelower electrodes 120 of the third MTJ elements are formed in thedielectric interlayers 122 and 126.

[0636] These contact holes can easily be formed by, e.g., forming aphotoresist pattern on the dielectric interlayer 126 by PEP and etchingthe dielectric interlayers 122 and 126 by RIE using the photoresistpattern as a mask. After etching, the photoresist pattern is removed.

[0637] In addition, a barrier metal layer (e.g., a multi-layer of Ti andTiN) 133 is formed on the inner surfaces of the contact holes by, e.g.,sputtering. Subsequently, a metal layer (e.g., a W layer) 134 thatcompletely fills the contact holes is formed on the barrier metal layer133 by, e.g., sputtering.

[0638] After that, the metal layer 134 is polished by, e.g., CMP andleft only in the contact holes. The metal layer 134 remaining in eachcontact hole forms a contact plug. In addition, metal layers (e.g., Talayers) 135 serving as the lower electrodes of the fourth MTJ elementsare formed on the dielectric interlayer 132 by sputtering.

[0639] [27] Fourth MTJ Element Forming Step

[0640] As shown in FIGS. 89 and 90, fourth MTJ elements 136 are formedon the metal layers 135. Each fourth MTJ element 136 has, as its mainportion, a tunneling barrier and two ferromagnetic layers that sandwichthe tunneling barrier, and has, e.g., the structure as shown in FIG. 7.

[0641] The lower electrodes 135 of the fourth MTJ elements 136 arepatterned.

[0642] The lower electrodes 135 of the fourth MTJ elements 136 caneasily be patterned by forming a photoresist pattern on the lowerelectrodes 135 by PEP and etching the lower electrodes 135 by RIE usingthe photoresist pattern as a mask. Then, the photoresist pattern isremoved.

[0643] After that, a dielectric interlayer 137 that completely coversthe fourth MTJ elements 136 is formed by CVD.

[0644] [28] Interconnection Trench Forming Step

[0645] As shown in FIG. 91, interconnection trenches 137A are formed inthe dielectric interlayer 137. In this example, the interconnectiontrenches 137A serve as trenches used to form read/write bit lines andextend in the Y-direction. If the metal layer material is Cu, sidewallinsulating layers (such as silicon nitride) are needed for preventingfrom Cu diffusion and corrosion are formed on the side surfaces of theinterconnection trenches 137A.

[0646] The interconnection trenches 137A can easily be formed by, e.g.,forming a photoresist pattern on the dielectric interlayer 137 by PEPand etching the dielectric interlayer 137 by RIE using the photoresistpattern as a mask. After etching, the photoresist pattern is removed.

[0647] The sidewall insulating layers can easily be formed by forming aninsulating film (e.g., a silicon nitride film) on the entire surface ofthe dielectric interlayer 137 by CVD and etching the insulating film byRIE.

[0648] [29] Ninth Interconnection Layer Forming Step

[0649] As shown in FIG. 92, a barrier metal layer (e.g., a multi-layerof Ta and TaN) 138 is formed on the dielectric interlayer 137, the innersurfaces of the interconnection trenches 137A, and the sidewallinsulating layers by, e.g., sputtering. Subsequently, a metal layer(e.g., a Cu layer) 139 that completely fills the interconnectiontrenches 137A is formed on the barrier metal layer 138 by, e.g.,sputtering or electroplating.

[0650] After that, as shown in FIGS. 93 and 94, the metal layer 139 ispolished by, e.g., CMP and left only in the interconnection trenches137A. The metal layer 139 remaining in each interconnection trench 137Aforms a ninth interconnection layer that functions as a read/write bitline.

[0651] An insulating layer (e.g., a silicon nitride layer) 140 is formedon the dielectric interlayer 137 by CVD. If needed, the insulating layer140 is polished by CMP and left only on the metal layers 139 serving asthe ninth interconnection layers.

[0652] Finally, for example, a dielectric interlayer (e.g., a siliconoxide layer) that completely covers the metal layers 139 serving as theninth interconnection layers is formed on the dielectric interlayer 137.

[0653] (3) Conclusion

[0654] According to this manufacturing method, a cell array structure(1-switch/n-MTJ structure) in which a read block is formed from aplurality of TMR elements stacked at a plurality of stages, and theplurality of TMR elements are independently connected to read bit linescan be realized.

[0655] In this example, to form an interconnection layer, the damasceneprocess and dual damascene process are employed. Instead, for example, aprocess of forming an interconnection layer by etching may be employed.

[0656] 5. Others

[0657] In the above description, a TMR element is used as a memory cellof the magnetic random access memory. However, even when the memory cellis formed from a GMR (Giant MagnetoResistance) element, the presentinvention, i.e., various kinds of cell array structures, the readoperation mechanism, and the detailed example of the read circuit can beapplied.

[0658] The structure of a TMR element or GMR element and the materialsthereof are not particularly limited in applying the present invention.In this example, the number of TMR elements in one read block is four.However, the number of TMR elements in one read block is not limited tofour and can freely be set.

[0659] As a read select switch of the magnetic random access memory, aMOS transistor, bipolar transistor, or diode is used. However, any otherswitch element such as a MIS (Metal Insulator Semiconductor) transistor(including a MOSFET), MES (Metal Semiconductor) transistor, or junctiontransistor can also be used as a read select switch.

[0660] According to the present invention, a magnetic random accessmemory having a new cell array structure suitable for an increase inmemory capacity and a manufacturing method thereof can be provided.

[0661] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. A magnetic random access memory comprising:memory cells which are stacked at stages to store data using amagnetoresistive effect; a read select switch which commonly connect toone terminal of each of said memory cells; and bit lines which arrangein correspondence with said memory cells and extend in a firstdirection, wherein each of said memory cells has the other terminalindependently connected to one of said bit lines, and said bit lines areelectrically isolated each other in read mode.
 2. A memory according toclaim 1, wherein said read select switch is arranged right under saidmemory cells.
 3. A memory according to claim 1, further comprisingcontact plugs each of which connects one terminal of one of said memorycells to said read select switch, and said contact plugs are overlappedeach other.
 4. A memory according to claim 1, further comprising asource line that extends in the first direction and is connected to saidread select switch.
 5. A memory according to claim 4, further comprisinga power supply terminal, and a column select switch connected betweensaid source line and said power supply terminal.
 6. A memory accordingto claim 4, further comprising a read word line which is connected to acontrol terminal of said read select switch and extends in a seconddirection perpendicular to the first direction.
 7. A memory according toclaim 6, wherein said read select switch is controlled by a row addresssignal.
 8. A memory according to claim 1, further comprising a read wordline which is connected to said read select switch and extends in asecond direction perpendicular to the first direction.
 9. A memoryaccording to claim 8, further comprising a decode line which isconnected to a control terminal of said read select switch and extendsin the first direction.
 10. A memory according to claim 9, wherein saidread select switch is controlled by a column address signal.
 11. Amemory according to claim 1, further comprising a read circuit, and acolumn select switch connected between said bit lines and said readcircuit.
 12. A memory according to claim 11, wherein said read selectswitch and said column select switch execute the same operation.
 13. Amemory according to claim 11, wherein said read circuit is constitutedby sense amplifiers arranged in correspondence with said bit lines andoutput buffers arranged in correspondence with said sense amplifiers.14. A memory according to claim 11, wherein said read circuit isconstituted by sense amplifiers arranged in correspondence with said bitlines, an output buffer which outputs one data of said sense amplifiers,and a selector which is connected between said sense amplifiers and saidoutput buffer.
 15. A memory according to claim 1, further comprising awrite bit line driver/sinker which is connected to two ends of each ofsaid bit lines to flow, to said bit lines, a write current in adirection corresponding to write data.
 16. A memory according to claim1, wherein said bit lines function as read bit lines and write bitlines.
 17. A memory according to claim 1, further comprising write wordlines which are arranged in correspondence with said memory cells andextend in a second direction perpendicular to the first direction.
 18. Amemory according to claim 17, wherein each of said write word lines isarranged on one terminal side of a corresponding one of said memorycells.
 19. A memory according to claim 1, further comprising blockselect switches each connected between the other terminal of acorresponding one of said memory cells and a corresponding one of saidbit lines.
 20. A memory according to claim 19, wherein said block selectswitch is controlled by a row address signal.
 21. A memory according toclaim 19, wherein said read select switch and said block select switchexecute the same operation.
 22. A memory according to claim 1, whereinsaid memory cells construct one read block, and data of said memorycells are simultaneously read.
 23. A memory according to claim 1,wherein each of said memory cells is formed from a magnetic memoryelement including a pinning layer having a fixed magnetizing direction,a storing layer whose magnetizing direction changes in accordance withwrite data, and a tunneling barrier layer arranged between said pinninglayer and said storing layer.
 24. A memory according to claim 23,wherein an axis of easy magnetization of said magnetic memory element isdirected in a second direction perpendicular to the first direction. 25.A memory according to claim 1, wherein said read select switch is formedfrom one of a MIS transistor, a MES transistor, a junction transistor, abipolar transistor, and a diode.
 26. A magnetic random access memorycomprising: memory cells which are stacked at stages to store data usinga magnetoresistive effect; a read select switch which commonly connectto one terminal of each of said memory cells; and bit lines whicharrange in correspondence with said memory cells and extend in a firstdirection, wherein each of said memory cells has the other terminalindependently connected to one of said bit lines, and storing data ofsaid memory cells are decided with according to directions of currentswhich flow in said bit lines.
 27. A memory according to claim 26,wherein said read select switch is arranged right under said memorycells.
 28. A memory according to claim 26, further comprising contactplugs each of which connects one terminal of one of said memory cells tosaid read select switch, and said contact plugs are overlapped eachother.
 29. A memory according to claim 26, further comprising a sourceline that extends in the first direction and is connected to said readselect switch.
 30. A memory according to claim 29, further comprising apower supply terminal, and a column select switch connected between saidsource line and said power supply terminal.
 31. A memory according toclaim 29, further comprising a read word line which is connected to acontrol terminal of said read select switch and extends in a seconddirection perpendicular to the first direction.
 32. A memory accordingto claim 31, wherein said read select switch is controlled by a rowaddress signal.
 33. A memory according to claim 26, further comprising aread word line which is connected to said read select switch and extendsin a second direction perpendicular to the first direction.
 34. A memoryaccording to claim 33, further comprising a decode line which isconnected to a control terminal of said read select switch and extendsin the first direction.
 35. A memory according to claim 34, wherein saidread select switch is controlled by a column address signal.
 36. Amemory according to claim 26, further comprising a read circuit, and acolumn select switch connected between said bit lines and said readcircuit.
 37. A memory according to claim 36, wherein said read selectswitch and said column select switch execute the same operation.
 38. Amemory according to claim 36, wherein said read circuit is constitutedby sense amplifiers arranged in correspondence with said bit lines andoutput buffers arranged in correspondence with said sense amplifiers.39. A memory according to claim 36, wherein said read circuit isconstituted by sense amplifiers arranged in correspondence with said bitlines, an output buffer which outputs one data of said sense amplifiers,and a selector which is connected between said sense amplifiers and saidoutput buffer.
 40. A memory according to claim 26, further comprising awrite bit line driver/sinker which is connected to two ends of each ofsaid bit lines to flow, to said bit lines, a write current in adirection corresponding to write data.
 41. A memory according to claim26, wherein said bit lines function as read bit lines and write bitlines.
 42. A memory according to claim 26, further comprising write wordlines which are arranged in correspondence with said memory cells andextend in a second direction perpendicular to the first direction.
 43. Amemory according to claim 42, wherein each of said write word lines isarranged on one terminal side of a corresponding one of said memorycells.
 44. A memory according to claim 26, further comprising blockselect switches each connected between the other terminal of acorresponding one of said memory cells and a corresponding one of saidbit lines.
 45. A memory according to claim 44, wherein said block selectswitch is controlled by a row address signal.
 46. A memory according toclaim 44, wherein said read select switch and said block select switchexecute the same operation.
 47. A memory according to claim 26, whereinsaid memory cells construct one read block, and data of said memorycells are simultaneously read.
 48. A memory according to claim 26,wherein each of said memory cells is formed from a magnetic memoryelement including a pinning layer having a fixed magnetizing direction,a storing layer whose magnetizing direction changes in accordance withwrite data, and a tunneling barrier layer arranged between said pinninglayer and said storing layer.
 49. A memory according to claim 48,wherein an axis of easy magnetization of said magnetic memory element isdirected in a second direction perpendicular to the first direction. 50.A memory according to claim 26, wherein said read select switch isformed from one of a MIS transistor, a MES transistor, a junctiontransistor, a bipolar transistor, and a diode.
 51. A magnetic randomaccess memory comprising: first and second memory cells which arestacked to store data using a magnetoresistive effect; a read selectswitch which connect to one terminal of each of said first and secondmemories; a first bit line which connect to the other terminal of saidfirst memory cell; and a second bit line which connect to the otherterminal of said second memory cell, wherein said first and second bitlines are electrically isolated each other in read mode.
 52. A magneticrandom access memory comprising: first and second memory cells which arestacked to store data using a magnetoresistive effect; a read selectswitch which connect to one terminal of each of said first and secondmemories; a first bit line which connect to the other terminal of saidfirst memory cell; and a second bit line which connect to the otherterminal of said second memory cell, wherein a storing data of saidfirst memory cell is decided with according to a direction of a currentwhich flows in said first bit line, and a storing data of said secondmemory cell is decided with according to a direction of a current whichflows in said second bit line.
 53. A read method of a magnetic randomaccess memory, the magnetic random access memory having a read blockformed from memory cells which are stacked each other and which storedata using a magnetoresistive effect, and sense amplifiers arranged incorrespondence with the memory cells, comprising: simultaneously andindependently supplying a read current to the memory cells in the readblock; detecting data of the memory cells by the sense amplifiers on thebasis of the read current; and simultaneously outputting data of thesense amplifiers.
 54. A method according to claim 53, wherein the dataof the memory cells are independently detected by the sense amplifiers.55. A method according to claim 53, wherein the other terminal of eachof the memory cells is short-circuited, and the read current flows forone terminal side to the other terminal side of each of the memorycells.
 56. A method according to claim 53, wherein the sense amplifierscompare a read potential generated from the read current with areference potential, thereby detecting the data of the memory cells. 57.A method according to claim 56, wherein the reference potential isgenerated using a resistive element having the same structure as that ofthe memory cell.
 58. A method according to claim 53, wherein when thedata of the memory cells are to be read, a ground potential is appliedto one terminal of each of the memory cells.
 59. A method according toclaim 53, wherein when the data of the memory cells are not to be read,one terminal of each of the memory cells is set in a short-circuitedstate, and the other terminal is set in a floating state.
 60. A readmethod of a magnetic random access memory, the magnetic random accessmemory having a read block formed from memory cells which are stackedeach other and which store data using a magnetoresistive effect, andsense amplifiers arranged in correspondence with the memory cells,comprising: simultaneously and independently supplying a read current tothe memory cells in the read block; detecting data of the memory cellsby the sense amplifiers on the basis of the read current; andselectively outputting one of data of the sense amplifiers.
 61. A methodaccording to claim 60, wherein the data of the memory cells areindependently detected by the sense amplifiers.
 62. A method accordingto claim 60, wherein the other terminal of each of the memory cells isshort-circuited, and the read current flows for one terminal side to theother terminal side of each of the memory cells.
 63. A method accordingto claim 60, wherein the sense amplifiers compare a read potentialgenerated from the read current with a reference potential, therebydetecting the data of the memory cells.
 64. A method according to claim63, wherein the reference potential is generated using a resistiveelement having the same structure as that of the memory cell.
 65. Amethod according to claim 60, wherein when the data of the memory cellsare to be read, a ground potential is applied to one terminal of each ofthe memory cells.
 66. A method according to claim 60, wherein when thedata of the memory cells are not to be read, one terminal of each of thememory cells is set in a short-circuited state, and the other terminalis set in a floating state.
 67. A manufacturing method of a magneticrandom access memory, comprising: forming a read select switch on asurface region of a semiconductor substrate; forming a first write wordline extending in a first direction on the read select switch; forming afirst MTJ element right above the first write word line; forming, rightabove the first MTJ element, a first read/write bit line which is incontact with the first MTJ element and extends in a second directionperpendicular to the first direction; forming a second write word lineextending in the first direction right above the first write word line;forming a second MTJ element right above the second write word line; andforming, right above the second MTJ element, a second read/write bitline which is in contact with the second MTJ element and extends in thesecond direction. wherein, out of said first and second write word linesand said first and second read/write bit lines, at least metal linesunder MTJs, are formed by a damascene process.
 68. A method according toclaim 67, wherein, out of the first and second write word lines and thefirst and second read/write bit lines, at least metal lines under MTJS,are formed by steps of forming an interconnection trench in aninsulating layer, forming a metal layer that completely fills theinterconnection trench, and removing the metal layer except that in theinterconnection trench.
 69. A method according to claim 68, furthercomprising, before formation of the metal layer, a step of forming abarrier metal layer. 70 A method according to claim 69, furthercomprising steps of, before formation of the barrier metal layer,forming a sidewall insulating layer on a side surface of theinterconnection trench, and after removal of the metal layer except thatin the interconnection trench, forming a cap insulating layer made ofthe same material as that of the sidewall insulating layer on the metallayer.
 71. A method according to claim 70, wherein the sidewallinsulating layer and the cap insulating layer are made of siliconnitride.